<nickoe>
mithro: That diagram you shared the other day with the riscv and mega project area. Is that a think that ties into the skywater-pdk, or is that purely related to the google offer to get a chip? Maybe it could be added to the readme to give an overview?
<tnt>
That's just how the google shuttle is organized.
<tnt>
If you want to constract skywater directly you can do whatever you want.
<nickoe>
ah ,ok
<mithro>
nickoe: Yeap - what tnt said
<Lofty>
Is there any way to get an approximate delay through paths given only Yosys synthesis output, or does that require a full place-and-route to get that information?
<Lofty>
While I know about ltp for unit delay, and the experimental sta command for Verilog specify timings, I don't know how to get timings from Liberty files
_whitelogger has joined #skywater-pdk
<nickoe>
tnt: I think I saw your "looking at skywater pdk" today
<nickoe>
tnt: Are you going to make a design for the shuttle?
<tnt>
Yup.
<nickoe>
tnt: What will you make?
<tnt>
RISC-V soc with support for fast spi flash/psram + hyperram (with 2 level cache) + USB core + ... Also will probably stuff some tests for USB HS phy in there and possibly some other analog stuff, depending on what other people will be working on.
<prpplague>
nickoe: i'm doing a replica of the 74181 and AM2901, i suspect neither will get accepted to the shuttle as there are way more interesting projects and only 40 slots
<prpplague>
nickoe: (you didn't ask, but i figured i'd comment)
<nickoe>
tnt: But will there be a possibilty for analog stuff at first?
<nickoe>
prpplague: Well, that is probably better than what I would ever be able to get time to. I am not reaallly familiar with those devices, but maybe they are more likely to work as expected?
<nickoe>
tnt: So will you reuse the riscv on the shuttle?
<tnt>
nickoe: no, the riscv on the shuttle we'll just use as a supervisor to manage muxing / disabling internal options.
<prpplague>
nickoe: 74181 is a classic 4-bit ALU and the AM2901 is the heart of the original AMD Bit-slice cpu stuff, all stuff that hasn't been manufactured since the mid 80's
<prpplague>
nickoe: well, that is part of the push here, is to test the sky30 pdk to see if it actually does what it is suppose to do
<tnt>
prpplague: Given that those would be very small compared to the 10 mm^2 you can try to stick them with another project and just have pin-muxing.
<nickoe>
tnt: OK. I have a hard time to grasp how much stucc can be stuffed into that chip. Also I am not really familiar with the size of the riscv stuff.
<prpplague>
nickoe: but yes, the operation of both chips is well know and easy to test
<prpplague>
tnt: yeah, that is what i was working on figuring out
<tnt>
nickoe: first results for a linux-ready VexRiscv was less than 1 mm^2 ...
<prpplague>
tnt: if i can do that reasonable with muxing
<tnt>
1 Mbits of SRAM is ~ 2 mm^2
<nickoe>
tnt: Will you be able to test your design completely on an FPGA?
<nickoe>
tnt: Ok.
<nickoe>
And how much area does the super projct have?
<prpplague>
nickoe: total silicon size is 16mm^2
<nickoe>
Also, it is unclear to me if only one chip is made. Aka one super project for all the ~40 projects?
<tnt>
Not entirely sure yet. Probably piece by piece. Thing is some blocks will have fixed clock relation ship that we might not be able to replicate in a FPGA.
<prpplague>
nickoe: of which about 10mm^2 is available
<nickoe>
tnt: What about under clocking it? Or what do you mean wiht the fixed clock relationship?
<tnt>
I mean, if we design the usb core to run at 96 MHz synchronous to the CPU core, you have to run it at that frequency ...
<tnt>
we can't run it slower in a fpga for testing because it wouldn't work ...