06:37 <mkk_> [Kunal Ghosh, skywater-pdk] @Channel Here's the beauty of 8-week-VSD internships. You can not only learn a scripting language, you can also implement a basic power analysis engine. Meet Charu Gupta, who, just like every VSD intern, learnt Python scripting from a VLSI application point of view. She also documented the whole demo to help other VLSI freshers/engineers and professionals on how to get started in Python scripting. *All o

06:37 <mkk_> https://www.vlsisystemdesign.com/opensource-power-analysis-tool-using-python-engine/

06:37 <mkk_> Just FYI - *Scripting is a MUST TO HAVE skill in VLSI industry*

22:33 <lkcl> Kunal: the entire Libre-SOC design is in python, and the coriolis2 layout P&R is also a hybrid of c++ and python. entirely parametric automated P&R down to GDS-II files

22:34 <lkcl> i would say that proper and full Software Engineering training is a must-have in the VLSI industry.

22:34 <lkcl> i was quite alarmed to learn that test-driven development (systematic and comprehensive unit tests at every level of the design) are not industry-standard practice.

22:35 <lkcl> many SoCs are developed first then top-level systems-only-level tested *after* all components are 100% completed.

22:36 <mkk_> [Dan Ravensloft, skywater-pdk] lkcl: I should point out that on Slack your name appears as "realname, http://irc.freenode.net"

22:36 <mkk_> [Dan Ravensloft, skywater-pdk] Anyway, formal verification can help with that kind of thing

22:39 <lkcl> Dan: wonderful :)

22:39 <lkcl> it does...

22:40 <lkcl> however again if it's only being applied at the top-level it doesn't help you find bugs in individual modules that you may not know you've gotten right/wrong

22:40 <lkcl> we use formal correctness proofs *as* both low-level module unit tests, and upwards

22:42 <lkcl> a formal correctness proof of bpermd for example:

22:42 <lkcl> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_bpermd.py;hb=HEAD

22:43 <lkcl> then a full pipeline formal correctness proof

22:43 <lkcl> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_main_stage.py;hb=HEAD

22:44 <lkcl> oh and then some "ordinary" unit tests on the pipeline

22:44 <lkcl> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/test/test_pipe_caller.py;hb=HEAD

22:44 <lkcl> *and* some more unit tests on the bpermd module (same directory)

22:45 <lkcl> then those pipeline unit tests are run from *two more levels up*