<mrdata>
i was thinking that a neuron is like a generic gate with a resistor network
<azonenberg_work>
i dont know neurology enough to know how they work lol
<mrdata>
where the resistor values can be modified
<mrdata>
basically, an axon fires when its chemical potential reaches a threshold; but synapses can enhance of inhibit this
<mrdata>
so analogously, a transistor will non-linearly amplify its inputs; the resistor network simulates the synapses
<mrdata>
^^ synapses enhance *or* inhibit, that is
<mrdata>
so, each generic gate generates a pulse when it fires; a transistor with a small capacitor on its output can do that
<mrdata>
and, neurons tend to fire spontaneously also; so pulse rate and timing is probably the more significant
<azonenberg_work>
hmm
<azonenberg_work>
I know there is work being done in the field but i'm not familiar with it myself
<mrdata>
i've read a few papers; most are either attempting to simulate artificial neurons in large AI frameworks in lisp, or studying precise behaviour of real life neurons in microbiological sense
<azonenberg_work>
i see
<mrdata>
but i havent seen attempts to build programmable gate arrays, of them yet
<azonenberg_work>
So you want to build an FPGA-like programmable brain?
<mrdata>
that would be nice
<mrdata>
the problem is, the connections architecture, which is of crucial significance, is unknown
<mrdata>
but, if the thing i build can be a physical manifestation of some of the artificial neural networks made with genetic algorithms, then the connections architecture can be decided by the genetic algorithms
<azonenberg_work>
Very interesting
<mrdata>
the important step will be, how to adequately represent the behaviour, both in an FPGA, and in a simulator
<mrdata>
so that they map
<azonenberg_work>
not sure if its possible in an fpga
<azonenberg_work>
this project sounds analog
<mrdata>
homecmos to the rescue
<mrdata>
goal: build and make scalable artificial neurons
<azonenberg_work>
lol
<azonenberg_work>
Worthy goal, just not an easy one
<mrdata>
indeed
<mrdata>
but this was predicted to occur; and so it should be done
<mrdata>
would be satisfied with a network of half a dozen axons, to start
<mrdata>
with re-programmable connections and strengths
<azonenberg_work>
You're probably talking a couple hundred transistors
<azonenberg_work>
definitely possible but at least a year out
<mrdata>
why not 6 transistors?
<azonenberg_work>
I'm assuming you will need a few more than that in order to amplify inputs
<cheater>
it's that simple only if you don't model channeling, receptors, etc
<azonenberg_work>
and act as resistors
<azonenberg_work>
then programmable drive strength will be a task in itself
<azonenberg_work>
probably means having four or five transistors that you can turn on one, two, three, four, or all
<azonenberg_work>
hooked up in parallel
<azonenberg_work>
And in any case i have yet to make even one working transistor
<azonenberg_work>
i havent even attemptd them as my MEMS focus has kept me from buying the materials
<mrdata>
bets each synapse is a small capacitor and resistor; and a single axon will have no more than 2 transistors
<azonenberg_work>
but a variable resistor or a fixed?
<mrdata>
since a not gate is modeled as a single NPN
<azonenberg_work>
and if you are doing cmos, remember you need two for everything as a push-pull
<azonenberg_work>
you generally cannot drive high and low with a single transistor
<mrdata>
the resistor and/or the capacitor may be variable
<azonenberg_work>
variable caps are highly nontriial
<azonenberg_work>
nontrivial*
<azonenberg_work>
variable resistors a bit less so, you have a big resistive element and transistors to short out each segment on request
<mrdata>
ok, i imagine fixed capacitance will do
<mrdata>
but R must be variable
<mrdata>
can be quantized
<mrdata>
to about 250 or so values
<azonenberg_work>
256? You can do that with whats basically an 8 bit DAC
<azonenberg_work>
or digital port
<mrdata>
ok
<azonenberg_work>
pot*
<azonenberg_work>
you have a N/2 ohm segment you can short out when r[7] is low
<azonenberg_work>
an N/4 ohm segment you short when r[6] is low
<azonenberg_work>
up to an n/256 ohm segment you short when r[0] is low
<azonenberg_work>
so eight transistors and eight resistive elements
<mrdata>
ok, so each neuron becomes a couple transistors for the axon, and an 8-bit DAC, and stuff, for each synapse
<azonenberg_work>
plus latches for each transistor to hold the on/off state
<azonenberg_work>
you are looking at eight switching transistors, eight D flipflops, and an 8-segment resistor
<mrdata>
ok. latched
<azonenberg_work>
or atlternatively, a sample-and-hold circuit (analog flipflop, pretty much)
<azonenberg_work>
and eight comparators
<azonenberg_work>
going to the transsitors
<azonenberg_work>
that way you can control the resistance by an analog input
<azonenberg_work>
You might even be able to have the S&H output go straight to the gate of a transistor operated inthe linerar region
<azonenberg_work>
linear*
<azonenberg_work>
and use it as the resistive element
<azonenberg_work>
that'd probably be the best option
<azonenberg_work>
So you have a capacitor, some kind of feedback circuit that compensates exactly for leakage by recharging as it leaks
<azonenberg_work>
and a single transistor
<azonenberg_work>
to form your latchable variable resistor
<azonenberg_work>
then one more transistor connecting your control input to the capacitor so you can charge or discharge it on demand
<mrdata>
and all these are in simplest possible elements that can be printed onto a die
<azonenberg_work>
transistors are easy, caps arent bad
<azonenberg_work>
not sure how the sample-and-hold works
<mrdata>
in real life, there are many synapses for each axon; 100:1 may be common
<mrdata>
but in a small device of half a dozen, full connection is 6:1 (including back-propagation)
<mrdata>
and these values should be brought to output. so about 6 inputs, 36 outputs, and some lines to program it
<azonenberg_work>
lol yes, that will be nontrivial to construct
<azonenberg_work>
Very interesting research project for sure
<azonenberg_work>
But my process is a couple years from being able to build it i think
<mrdata>
noted
<mrdata>
i will try breadboarding it first, ithink
<mrdata>
just to verify the circuitry on a small scale
<mrdata>
it will be important for the simulator to give pretty-close to identical results to the physical device
<mrdata>
otherwise the connections architecture cant be evolved
<azonenberg_work>
You will likely have to train on the physical hardware
<mrdata>
yes
<azonenberg_work>
especially if using a homebrew process with lots of variation between parts
<azonenberg_work>
the device's little variations will become almost a part of the program
<mrdata>
i expect they will, yes
<mrdata>
so, so long as the variations are "small enough" that they may be compensated-for with minor training, the connections architecture will be common to both simulator and physical device
<azonenberg_work>
Well, i suggest that you test it out on a breadboard because its quite a ways from being IC-able
<azonenberg_work>
at least on my process
<azonenberg_work>
I'd love to see results
<mrdata>
sure. i can throw these ideas into a circuit simulator even before that
<mrdata>
even before i spend $ on parts
<azonenberg_work>
yep
<mrdata>
cant promise timing, but i have some time before xmas