azonenberg changed the topic of #homecmos to: Homebrew CMOS and MEMS foundry design | Wiki: http://homecmos.drawersteak.com/wiki/Main_Page | Repository: http://code.google.com/p/homecmos/ | Logs: http://en.qi-hardware.com/homecmos-logs/
<berndj> are real-life multiplexers (as part of a bigger chip) purely combinational or do they play tricks with enabling/disabling one of the inputs onto a common bus?
<azonenberg> berndj: i assume it varies
<azonenberg> for very wide muxes i'd imagine tristating is common
<azonenberg> (as in lots of inputs, not many bits wide)
<berndj> is 3-bits select (to select 1 from 8) "very wide"?
<azonenberg> I'm not sure what the threshold is
<azonenberg> all of the ones i do in FPGAs are purely combinatorial
<azonenberg> but thats because there aren't internal tristates
<berndj> i'm not really sure what the point to all this polygon doodling is but it feels educational
<azonenberg> lol
<azonenberg> i'll be doing my share of that in six months or so
<azonenberg> i'm planning to take vlsi in the spring
<berndj> do you get to make your very own cpu?
<azonenberg> No, that class mostly works at the cell level and below
<azonenberg> advanced computer hardware design aka ACHD works at the RTL level and i took already
<azonenberg> there's also one on designing standard cell ASICs that's rarely offered due to lack of faculty and demand from the student body
<berndj> so yeah, i'm trying to decide between multiplexing one of 8 registers onto a logic pipeline, or whether to circulate those 8 registers in a ring and run the logic off a fixed tap
<berndj> "standard cell ASICs" - does that imply there's such a thing as ASICs that don't use standard cells?
<azonenberg> Sure
<azonenberg> anything analog :p
<berndj> i meant digital :)
<berndj> those 4004 masks looked pretty random to me, but maybe that's because non-cmos just is random like that - you don't need complementary logic the be adjacent (or anywhere)
<azonenberg> that's NMOS, and yeah
<azonenberg> that was also hand drawn
<azonenberg> not standard cells
<azonenberg> or was it PMOS?
<azonenberg> i forget
<azonenberg> i know it was a single MOS family
<berndj> i vaguely recall PMOS for that early stuff
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<berndj> how about this crazy idea: a pipeline of n-wide half adders, and keep circulating the carries back as addends until the carry vector is zero?
<Sync_> wat
<berndj> it looks like most 32-bit additions would complete in 4-6 cycles
<berndj> Sync_: i'm trying to come up with a power-efficient way of adding numbers
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