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<anarsoul>
robmur01: any ideas whether ATF sources are available for this binary?
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<flacks>
I'm using upstream ATF and U-Boot, and composing the pre-bootloader via the rkbin binary DDR and miniloader, and although boot takes 2-3 minutes and there is a soft lockup every time, reboot does work.
<flacks>
so it'd seem like the problem lies in upstream idbloader
<anarsoul>
probably an issue with memory init?
<flacks>
using the blob idbloader also allows for setting macaddr via setenv, too, FWIW
<flacks>
hm I have been trying both vanilla upstream and that custodian repo
<flacks>
let me try once again
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<flacks>
yep, seemingly the same as with vanilla u-boot.
<flacks>
interestingly, from the time linux does the reboot dance until u-boot output, it takes upwards of 10 seconds, whereas with the blob idbloader, reboot is almost instantaneous
<anarsoul>
flacks: heh
<anarsoul>
apparently you don't use my patch for ATF
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<flacks>
ah, indeed
<anarsoul>
flacks: with this change it gets into u-boot instantaneously, but linux still may (or may not) hang
<micken>
robmur01: acordinng to 3399 , the are_option is disabled (assume that is gicv2 compat)
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<flacks>
anarsoul: indeed works, thank you very much :)
<anarsoul>
flacks: does linux still hang for you?
<flacks>
yes
<anarsoul>
:(
<anarsoul>
I kind of hoped that newest rockchip patches fixed the issue
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<flacks>
:\
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<micken>
robmur01: I think I want to disable affinity and use gicd_targetr instead
<micken>
robmur01: gicd_ctrl can disable it , but I wonder how many secure layers theer are?
<micken>
robmur01: I also wonder which cpu number that is a72 in targetr..? There are four fields , and each field can have 0-7
<micken>
as a follow up , the offset for gicd_target is offest + 4*n
<micken>
so I setit when I enable a interrupt
<micken>
A72 doesn't get interrupted
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<micken>
sigh , writing to itargetr , read back still 0x0
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<micken>
for some reason a72 probably aren't participapting
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<micken>
back to affinity and route, but the above problem still aplies , I dont care about the aff fields , just using bit 31..
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<robmur01>
micken: as I alluded to before, the affinities for ARE should be the same as the CPU MPIDR_EL1 affinities (as read from EL2)
<robmur01>
my knowledge of IRM (bit 31) is mostly just that it's a whole other can of worms, but AIUI delivering interrupts to CPU0 is a perfectly valid outcome of that mode
<robmur01>
oh, and the meaning of "are_option" is, confusingly, "*don't* include compat mode" - I did look up the integration manual to check ;)
<robmur01>
flacks: if you're using the miniloader, then you really want to hack rkclk_init() from SPL into u-boot main stage (where the downstream u-boot does it)
<robmur01>
missing that is the reason for the 3-minute boot time, and might possibly account for some other wonkiness too
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<micken>
from 32bit , mpidr is set bit 31 and bit 8
<micken>
I don't know how core numbering works in cluster , is A72 core0 core 4?
<micken>
it was represented by 0x100 in the smc call for cpu_on
<micken>
my first try with smp system :)
<robmur01>
for RK3399, aff1 is the cluster (0 = little, 1 = big) and aff0 is the core number (0-3 or 0-1 as appropriate)
<micken>
oh thanks
<micken>
setting irouter to 0x100 didnt help (bit 8 , for big) and 0 for core 0
<micken>
robmur01: but thanks for explaining how the aff regs worked
<micken>
robmur01: GICD_CTLR ,, in the manual it is described in three ways
<robmur01>
micken: unless you're hacking on ATF, assume you have the Non-Secure view of everything
<micken>
yes
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<maz>
micken: make sure you're changing the affinity with the interrupt disabled, and then poll for RWP in the distributor.
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<micken>
maz: ok disabling all interrupts, wait for rwp ( or should it be done between each disable?) and set affinity to all interrupts (0x100)
<micken>
gicd_ctrl is 0x37
<micken>
I am in 32bit el1_(ns)
<micken>
btw is router reg 0x6000 or 0x6100 ( it differs from list to description)
<maz>
micken: it depends on which interrupt you're routing.
<maz>
micken: the architectural way to chance the affinity is "disabled the interrupt to want to reroute; change affinity; if was enabled then re-enable; in any case wait for RWP to clear.
<micken>
maz: I want all interrupts from 32 and up to have same affinity..
<maz>
micken: then you do the above for each of them.
<maz>
0x600 is the base for all interrupts, but the first 32 are located in the rdists, so the 32 first registers are RES0
<maz>
INTID32 is at 0x6100, and up it goes.
<micken>
I do , I think , but I wait for rwp after setting affinity (loop), maybe doing it after every disable :)
<micken>
one thing that bugs me is that I get a el3 excpetion as soon as I poke or peek group0
<micken>
for the single core a53 system I do this to ack a irq: MCR p15,0,a1,c12,c12,1
<micken>
where a1 is irqid
<micken>
but from what I can see that is grp1
<micken>
that ack is a possible error , if the cpu interrupts but nothing acks , it will stall interrupt wise
<maz>
in NS, you can only have group1 interrupts
<micken>
ah I see
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<maz>
micken: that is, unless you start playing with DS and clear FIQ from SCR_EL3. not worth it.
<micken>
:)
<micken>
How do I know that irqs not end up in group0?
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<maz>
micken: that's for the secure side to decide.
<maz>
micken: secure delegates interrupts to non-secure. you don't get to choose.
<micken>
ok
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<micken>
I feel that I miss some switch on thing :) Interrupts gets enabled thats for sure
<micken>
and it worked on bootcore
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<micken>
the distributor is at offset 0x0 , right?
<micken>
in previous cases 0x1000 was a common GICD start
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<micken>
yes it is at start
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<mickenx>
iiiiipad chat
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<mickenx>
maz: if you look at that mem dump i linked, does it make sense? tha afinity setting is written in every other word, a thing because of the *8
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<mickenx>
is there some limitation with timers versus cores that i need tothink of. the first irq i want to see is from timer0