15:38 <robmur01> mickenx: the VOPs don't have a dedicated regulator, they're in the "logic" voltage domain along with most of the other peripherals. They do have their own power domain though (as does HDMI), which might possibly need attention if you're not fresh out of reset

15:38 <mickenx> robmur01: thanks for answering

15:39 <mickenx> robmur01: if they are the same in pmic , I think I have it right as the hdmi phy is working

15:40 <mickenx> robmur01: what is hclk , and do I need to connect that to a pll?

15:40 <mickenx> robmur01: right now I use vpll for pixelclock and cpll for aclk

15:41 <mickenx> robmur01: fancy looking at my hacky driver?

15:41 <mickenx> all assembler

15:41 <robmur01> hclk is usually the AHB clock for the actual register interface - if that's not running chances are you'll just deadlock trying to read/write anything

15:42 <mickenx> robmur01: alright there is a divder for it .. so I thought it might need some setting

15:43 <mickenx> the symptons I get feels like timing issues

15:43 <mickenx> IF i double xres I always get nice text on the console.. but that s not a solution

15:44 <mickenx> not double in vop, but change the cru reg ( I guess now , not having it in front of me ) 1c4

15:45 <robmur01> I have no experience with the VOP itself (or any other display hardware, really), more just a "big picture" understanding of hardware integration in general ;)

15:45 <mickenx> ok!

15:45 <mickenx> Well , thanks for the input