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<icenowy[m]>
is there any way to capture all MMIO access to a peripheral?
<icenowy[m]>
I think I will need this to implement proper H6 PCIe support
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<smaeul>
icenowy[m]: yes, the usual way is to run the program in a virtual machine that traps the MMIO access, records it, and forwards it to the host device
<awais>
+
<smaeul>
depending on how low-level this needs to be (and how important to the host the MMIO space is), you may need to run the program doing MMIO on another machine, and forward MMIO accesses over UART or some other connection
<smaeul>
of course, there's also JTAG
<smaeul>
If you only need to trace a couple of registers, and they read back the same as whatever you write, you could also poll them from AR100
<montjoie>
BenG83: mostly compatible, the tasklist size element changed from cryptlen/4 to cryptlen
<montjoie>
some more register write for start task
<montjoie>
the most cryptic is the new RAES "algo"
<montjoie>
so now I have two way of doing AES (and XTS is exclusive to RAES)
<Pe3ucTop>
Could anybody suggest SPI-DMA test program ? I find spi-test , but I doubt if it could help with DMA transfers ?
<Pe3ucTop>
small correction, curently using spidev_test and modified version of it, did not find anything related to DMA nor in spidev source, nor in spidev_test .
<mripard>
it's normal
<mripard>
whether to use DMA or not is a kernel policy
<mripard>
it shouldn't be exposed to the userspace, nor that the userspace care about it
<Pe3ucTop>
mripard: thanks for respons, I was waiting for such answer :) , I understand that DMA is at kernel level and is used by drivers directly. I would like any suggestions for easy testing DMA capability of SPI .
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<mripard>
any thing doing SPI traffic is good enough then
<icenowy[m]>
smaeul: I mean capture it in a running kernel and redirect to a driver
<mripard>
an EEPROM driver, an spidev-based application
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<Pe3ucTop>
mripard: thanks, so if I use spidev for example 2kb transfer, it going use DMA when it's possible ? Is it correct ?
<icenowy[m]>
I need to set the PCIe MMIO page register when accessing PCIe MMIO space
<icenowy[m]>
I don't know why Allwinner uses such a strange design
<mripard>
Pe3ucTop: yes
<icenowy[m]>
mripard: BTW for the H6 PCIe problem do you have any idea to implement it?
<icenowy[m]>
Allwinner BSP modifies the driver to make it work
<mripard>
icenowy[m]: I have not followed the discussion at all, sorry
<mripard>
is it all on IRC ?
<icenowy[m]>
not all, some only exists in my mind
<icenowy[m]>
I think I should explain here
<icenowy[m]>
the PCIe hardware on H6 is quirky as only the DBI (root complex) space is always accessible
<icenowy[m]>
for config space and {MM,}IO space, only 64KiB can be accessible at the same time
<icenowy[m]>
to access an address, the high 16-bit of the address must be written to a register in DBI
<mripard>
from what my colleagues who worked on PCIe are telling me, it breaks a few assumptions in how PCIe works
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<icenowy[m]>
what?
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<mripard>
all drivers expect an IO space where they can readl/writel to
<mripard>
you wouldn't be able to change the memory window you can see without modifying all drivers
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<icenowy[m]>
mripard: is wrap all IO with MMU possible?
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<mripard>
icenowy[m]: that would not solve the issue that you need to move that window when you want to change the 64k you want to access, would it?
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<icenowy[m]>
mripard: yes
<icenowy[m]>
ths issue still exists
<icenowy[m]>
but if only the current 64k is mapped, page fault can be caught to remap the memory, right?
<mripard>
you don't need an IOMMU to do that
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<mripard>
you can do it with an MMU
<mripard>
but that will destroy the performances
<icenowy[m]>
yes but it's the only generic way
<mripard>
maybe you should send an email to the PCIe maintainers
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<miasma>
tkaiser: i don't see the name on the list of random names. so it seems quite unlike. they'd have to sell one hundred boards to cover the costs
<miasma>
*unlikely
<KotCzarny>
i suspect they sell a lot more than that
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<jernej>
tl_lim: nothing from my side for now, except if there is a possibility for wayland mali
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<tl_lim>
Noted, wayland is the $$$ question. I will bring up this request.
<jernej>
tl_lim: is there any chance that AW would release new revision of H6 with fixed PCIe? :)
<tl_lim>
actually I get in the process on getting SDK ver 1.1 for icenowy, which have the PCIe driver implementation.
<tl_lim>
I should abel to get in with 24 hours time.
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<smaeul>
interesting thing about A64/H5: CPU0 isn't in its own power domain, like on earlier and later SoCs (note the lack of a switch in the diagram in the manual)
<smaeul>
pwroff_gating bit 0 turns off the whole cluster, like a83t; but bit 4 does nothing, unlike a83t
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<Ixnus>
tl_lim: what about some VE info ?
<smaeul>
hmm, I guess I should say "clock domain", since it's separate clock gating that it's missing (the power switch works the same as other SoCs)
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<jernej>
mripard: I tested CEC on A83T and H3 and it works.
<jernej>
however, it depends on the board how good
<jernej>
for example, on BananaPi M3 (A83T) and OrangePi 2 (H3) works great
<jernej>
but on OrangePi Plus 2E it looked like one way communication
<jernej>
I could turn on and off TV, but I couldn't receive any keys
<jernej>
I didn't test it on H5 yet, but I assume it's same as on H3
<tl_lim>
@Ixnus, I will check on VE info.
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