<libv>
jemk: source for the dma engine, or disp code?
<jemk>
wens: as far as i understand this, tcon can get its frame data from the "global" dma engine, dedicated dma chanel 0xe/0xf
<libv>
wens: so we have the dma channel descriptor structure from code, right?
<wens>
in the A23 LCD controller, there is input for DMA RGBA888 and RGB565, so at least the newer one does
<wens>
the diagrams in the datasheets have a DMA channel from memory to the LCD controllers, though I haven't been able to find the register value for that mux
<Montjoie>
Turl, yes interested on DMA
2014-06-02
<Turl>
Montjoie: you were interested on DMA on mainline, weren't you?
<marcin_>
ssvb: BTW It is first time, when I can see passing DMA address in "bit" unit...
2014-05-27
<codekipper>
yeah..I need dma so I'm stick sticking with 3.4
<mripard>
[ 0.017155] DMA: failed to allocate 256 KiB pool for atomic coherent allocation
<Turl>
wens: [ 0.052974] edma-dma-engine edma-dma-engine.0: Can't allocate PaRAM dummy slot <- maybe it registers too early? why is it even probing?
<wens>
with multi_v7_config, maybe something overrided the DMA API
2014-05-26
<oliv3r>
what I want for xmas now is, dma enabled NAND on an A10
<shineworld>
what could change a script.bin level (I guess in dma timings or like that)
2014-05-23
<oliv3r>
mripard: the life of the product will be a few years :p can't be on 3.4 oall of it, and can't use mainline just yet as we need nand + dma; the final product won't ship till nov - feb so there is still time
2014-05-22
<mripard>
for DMA, see with Turl_
<oliv3r>
i'll buy you all cake if nan enabled DMA is available in august :)
<oliv3r>
mripard: you commited the SPI and DMA stuff to a10/a20 too?
<mripard>
it has DMA
<oliv3r>
mripard: but in all seriousness, does A31 have DMA + Nand? I'd expect DMA only?
<oliv3r>
mripard: a31 has nand + dma?
<oliv3r>
though DMA maight be crucial :(
<oliv3r>
bbrezillon: what's the nand status? do we have dma enabled nand driver?
2014-05-19
<wens>
codekipper: I'm hoping sun8i DMA will only just be a few tweaks away from sun6i
<Turl>
codekipper: I'm working on DMA as we speak btw, just starting and getting soaked in
<codekipper>
Started looking at mainlining audio work but don't think I'll be able to get very far without Turls DMA
<mripard>
wens: yes, but some IPs can only use the normal DMA
<wens>
mripard suggested normal DMA can only do one request/channel at one time
<wens>
Turl: I was thinking the DMA driver for A10/A20 could be split into 2 parts, and we'd implement the dedicated DMA channel part first
<wens>
ddc: sound drivers depend on dma driver first, otherwise you'd get choppy audio
<hani>
bbrezillon >> I don't understand the need for the DMA. Is it going to speed data transfer have you done any comparison
<bbrezillon>
BTW, I'd like to change the HW ECC layout, so that we can later move to DMA transfer if we need/want to
2014-05-16
<plaes>
DMA \o/
<mripard>
mostly DMA for the A10/A20, and bringup of the A23
2014-05-09
<codekipper>
DMA on A10/A20.....it's been mentioned that you're doing this during Gsoc
2014-05-06
<codekipper>
I've started looking at audio mainlining but with the lack of DMA I didn't get very far.
<ccaione>
codekipper: mripard already submitted some patches about DMA IIRC
<codekipper>
I'm thinking about looking into the DMA on A10/A20
2014-05-05
<Montjoie>
Wizzup, no DMA engine yet
<Wizzup>
Well, I saw a mention of DMA, but if you're not using DMA there needs to be a way to 'feed' the data to the SS?
<Turl>
Montjoie: PIO or DMA?
2014-05-02
<montjoie[home]>
with the 3,4 kernel, the DMA was usefull only for request > 4k
<Wizzup>
hypothalamus: probably with DMA, I guess
<montjoie[home]>
I expect better perf when DMA would be availlable
2014-04-25
<wens>
emac has no dma, bad performance
2014-04-03
<wens>
wingrime2: GMAC has it's own DMA controller
<wingrime2>
mripard: GMAC need dma?
2014-03-28
<wingrime2>
mripard: dma used for sound, nand ,..
<wingrime2>
mripard: err, As I remebere disp not need dma ??
<mripard>
especially since we still don't have the DMA on the !A31
<geecko>
rz2k, we're trying to switch to dma-buf on the exynos4 kernel
2014-02-15
<ssvb>
lioka: it gets handled before dma_contiguous_reserve
2014-02-12
<kenny>
It looks like the Pis have seem some of these and they go away with their options 'sdhci-bcm2708.missing_status=0' and 'sdhci-bcm2708.sync_after_dma=0'. Is there anything similar?
2014-02-10
<bbrezillon>
Nyuutwo: Hi, I'm the one currently working on the NAND driver, and for the moment it does not depends on DMA (I might add support for DMA transfers later)
<Nyuutwo>
afair nand depends on dma
<Nyuutwo>
oliv3r: and how is DMA?
2014-02-07
<libv>
anyway, whatever you cedrus guys do, aim for dma-buf/dma-fence
2014-02-06
<wens>
gzamboni: the A23 DMA driver seems to use proper DMA engine API?
<gzamboni>
dma is kind of complex, i cant fully understand, but its what we need to keep going with all other stuff
<arokux>
gzamboni: so are you working on dma for A10/A13/A20?
<arokux>
gzamboni: hi, they say you work on dma?
<gzamboni>
the dma /sound /spi code and registers from the A23 sdk are quite different then for the A10 /A13 and A20 SoCs
<wigyori>
quick question - so the nand and the sata driver runs without dma so far, right?
<oliv3r>
sound requires DMA :(
<oliv3r>
arokux: dma is probably not that easy though :)
<arokux>
wens: who is looking at dma?
2014-02-05
<wens>
someone is looking at DMA
<wens>
but need DMA first
<wens>
mripard: personally I'd like this as the default in the dtsi, anyone working on the emac, say for DMA, can override it
2014-02-04
<gzamboni>
mripard, later today i will clean up my dt work on the dma code and send you
2014-01-28
<libv>
ssvb backported dma-buf to staging btw
<libv>
it will end up using dma-buf/dma-fence, so work towards that and it will somehow converge
2014-01-23
<libv>
wingrime/nove: please use dma_buf/dma_fence
<libv>
so perhaps g2d will remain as is, it will need to get dma_buf and the afterthought (wtf!) that is dma_fence
2014-01-22
<wens>
looking at otg driver from 3.0 and from A23-3.4, A23 has new DMA registers, whatever that's for
2014-01-21
<Turl>
oliv3r: mainline doesn't have disp nor dma nor audio
<Turl>
there is no /dev/ node for dma that I know of
<Turl>
gzamboni: well, the dma engine is the device right?
<gzamboni>
oh, ok, but generally we dont have devices for dma , do we ?
<gzamboni>
wens, he did sent a patch for spi without dma, but its only for A31
<wens>
Montjoie: mripard_ plan is to get SPI working first, then work on DMA with SPI as testbed
<Montjoie>
gzamboni, you work on the DMA engine ?
<gzamboni>
hey, im getting a probe error in my dma controller driver ( sunxi_dmac: probe of sunxi_dmac failed with error -22 ) any idea of how can i debug and find from where does it comes from ? i used somes printk but it seems to pass everything
2014-01-20
<gzamboni>
Turl, yes like this: interrupts = <26>; in the dtsi file, i added a subnode for the dma, i'm playing around with the dma code from the sdk's linux 3.4 kernel of a23
2014-01-16
<libv>
oliv3r: i think this just another bit of dma code that was copied
<oliv3r>
libv: since the aw dma engine driver from the old stuff is printing simtec copyright
<oliv3r>
btw, simtec electronics; is that the IP used for the DMA engine? or is it AW 's own with simtec being some pseudo name
2014-01-15
<bbrezillon>
I managed to get this working without DMA access
<bbrezillon>
I'm not using DMA at all
<slapin_>
bbrezillon: too bad, but how do you test it then as there is no DMA support in mainline yet?
<slapin_>
bbrezillon: does it work without DMA?
<mripard>
I have SPI working since yesterday, so I guess I'll work on DMA in a few days
<mripard>
slapin_: the plan has always been to merge SPI with PIO, to later use it to debug DMA
<slapin_>
mripard: do anybody actively working on DMA support?
2014-01-14
<gzamboni_>
well now i have to port the spi and change the fex get functions to dts to test the dma
<gzamboni_>
i did manage to compile the dma code on 3.10
<gzamboni_>
they use some includes and stuff that are not present in 3.4 like virt-dma.c / virt-dma.h that were up only in v 3.6
<oliv3r>
as we have spi there; dma engine, wwhile really nice, won't that be a lot of work?
<oliv3r>
gzamboni_: i was talking about sun4i_cedar, you about dma and spi
<gzamboni_>
oliv3r, i'm trying to port the dma and spi code from the A23 sdk to the experimental/sunxi-3.10 branch. i have some questions like how should i organize the plataform data
2014-01-13
<bbrezillon>
yes, I heard DMA is not supoorted in mainline yet
<oliv3r>
DMA probably relies on DMA engine anyway
<bbrezillon>
still no DMA
<oliv3r>
bbrezillon: still a basic driver with no ecc and no dma right? (which is fine, just curious)
2014-01-12
<hramrach>
it's pretty much all DMA once you get some baseline CPU performance which most CPUs do meet today
2014-01-11
<wingrime>
rz2k: have you saw new AW dma engine driver?
<rz2k>
and all the channels from the softwinner dma
<rz2k>
hani: I read that they dont use DMA and HW ECC
2014-01-10
<oliv3r>
slapin_: bbrezillon started to commit a simple (no dma no ecc) mtd driver to the ML i think
2014-01-08
<oliv3r>
bbrezillon: in any case, a slow, well working driver without DMA and ECC for now is far preferable then the nothing we have now :)
<bbrezillon>
oliv3r: I'm not using DMA transfers, this should solve the problem
<bbrezillon>
oliv3rI'm not using DMA transfers,
<bbrezillon>
DMA not enabled -> CPU is not offloaded when writing from/reading to NAND
<bbrezillon>
my proposal is a lot more simpler, and does not implement all the NFC features (HW ECC, DMA, HW randomization, ...)
<perr>
i dont know how to conf the DMA for this
2014-01-07
<jemk>
and in mainline, as far as i understood it, one can use dmabuf for that, passing dma buffers between different drivers
2014-01-06
<oliv3r>
mripard: i've started documenting how the BROM does SPI but they do the whole DMA thing there even;
2014-01-03
<oliv3r>
woprr: that should be cool; i take it the TS driver will require dma?
2014-01-02
<wingrime>
oliv3r: best thing also, that all dma related drivers now use dma engine
2014-01-01
<wingrime>
wens: but dma end device address id need be same with soc's
<wingrime>
wens: as I see dma IP looks same
<wingrime>
wens: thats 3rd version of dma driver from aw
<wens>
it seems 3.3 driver doesn't use DMA engine API, but there is a driver under mach-sun?i
<oliv3r>
so how where we missing DMA engine driver? how was it done with 3.3?
<wingrime>
mnemoc: so, new a23 kernel have nice dma-engine driver
<wingrime>
hramrach: also, looks sound are adapted to new dma
<hramrach>
Still I have to ask what actually uses the dmae since pretty much all drivers are now in-tree because they use a private dma controller
<oliv3r>
wingrime: n01 is working on axp; maxime on spi + dma
<wingrime>
oliv3r: whats up with dma and axp in mainline?
2013-12-31
<mrnuke>
Intel southbridges contain an ARC code. it runs out-of-band with the OS, survives system resets, can emulate virtual PCI devices, has full DMA access to memory, and
2013-12-30
<spv>
like resetting the DMA necessarily reset the PHY
<spv>
I was wondering if resetting the DMA, in the core, required that it communicate with a PHY or something ...
<spv>
i.e. would the DMA resetting depend on the pin mux state?
<spv>
wens: did you ever run into issues with the GMAC where the DMA would refuse to reset?
<spv>
Have any of you guys gotten the error "stmmac_open: DMA engine initialization failed" upon boot, in relation to the gmac?
<wens>
Turl: it has a dedicated DMA controller. AFAIK it does a DMA burst for each packet
<Turl>
wens: is it using DMA or PIO btw?
2013-12-24
<mnemoc>
oliv3r: it's somhow like DMA
2013-12-23
<wens>
my optmistic view is we could take another DMA driver and modify it to our use
<Montjoie>
I look forward any work on DMA
<wens>
oliv3r: didn't he say he was going to do DMA?
<oliv3r>
this SPI stuff is more work then I expected, as it does rely on DMA
<oliv3r>
hah! see! you can do DMA on the SRAM
<wens>
oliv3r: it can, you have to set the src/dst type in the dma controller
<oliv3r>
the SoC can use DMA using SRAM just fine, can it not?
<oliv3r>
it looks like the SPI controller is here being set up to transmit data via dma
<oliv3r>
wens: just trying to understand what it's doing with the DMA controller
<oliv3r>
wens: i'm thinking dma setup atm still
<wens>
oliv3r: my impression was that you had to tell the dma controller to start
<oliv3r>
wens: and then whenever i write something to memory (that is dma mapped?) it will directly put that into the SPI0_TXDATA register, correct? so i can simply copy something to ram, and that gets transmitted (via dma)
<oliv3r>
wens: if i'd setup DMA 'somehow' (for SPI in this example) I basically say DMA_DESTINATION_ADDR = SPI0_TXDATA
<oliv3r>
stupid SPI code sets up DMA stuff int he BROM :(
<wens>
oliv3r: DMA docs? only the registers i think
<oliv3r>
wens: we have very little DMA docs don't we?
2013-12-20
<oliv3r>
Turl: if they would have used DMA, do they need the interrupt to signal that a dma packet is ready?
<oliv3r>
Turl: but how do you do DMA if the memory controller is not enabled yet?
<oliv3r>
Turl: they even go as far as setup specific dma registers in the SPI DMA Controller register
<Turl>
oliv3r: yeah that's dma
<oliv3r>
(the DMA gate in CCM)
<oliv3r>
Turl: why would anything enable DMA as early as the BROM?
<oliv3r>
so this can't even be DMA related; as we don't have ram
<oliv3r>
i also don't get why/how the BROM is enabeling DMA mode, since we don't have setup the ram controller at all
<wens>
for DMA , you tell the controller source and destination address, burst length, and let it do its magic
<oliv3r>
wens: see I don't know at all how DMA works
<oliv3r>
the above asm was setting up the DMA of the SPI
<wens>
oliv3r: DMA?
<oliv3r>
wens: can I pick you rbrain with regard to DMA?
2013-12-16
<libv>
dma_alloc_coherent works for large allocations too
<ssvb>
and yes, it's good that we have CMA for dma_alloc_coherent in the newer kernels (but at least it works for large allocations)
<ssvb>
dma_alloc_coherent is good for allocating a large pool, but not for small allocations inside of it
<libv>
dma is sadly only really aimed for "small allocations"
<libv>
ssvb: now, i was about to state that perhaps we can convince this dma allocator to use a single large reserved space
<libv>
ssvb: this is why i am using dma_alloc_coherent
<libv>
ssvb: i am sure that dma_alloc_coherent will be acceptable upstream
<libv>
ssvb: i am using dma_alloc_coherent for disp
<libv>
but dma doesn't allow for that, and i am not sure cma will be any better as it is just some layer on top of that
<libv>
and imho cedar, g2d and disp should share dma space
2013-12-13
<wens>
torbenh3: that was a dma mode issue. forcing store & forward fixed it
2013-12-11
<libv>
ssvb: dma_buf should go some way
2013-12-10
<ssvb>
Turl: still it's an interesting patch, because it might speed up migrating the buffers between CPU/GPU, and the things involving the use of DMA
2013-12-09
<wens>
IIRC, the only tweaks to dw were dma burst length
2013-12-06
<Montjoie>
for the moment a dd of 250M on a dm-crypt relying on tmpfs is writed in 23s without SS and in 33s with SS (37 with DMA)
<ssvb>
torbenh3: there will be no free cpu without using dma for dm-crypt
<ssvb>
Montjoie: ouch, this sounds painful, does it have any advantage over purely software encryption without dma?
<Montjoie>
wens, dm-crypt crypt with buffer of 512bytes, too small for having any performance increase with DMA vs SS CPU mode
<wens>
Montjoie: dm-crypt doesn't use DMA?
<Montjoie>
I need info on DMA only for optimization
<Montjoie>
wens, yes it can work without it, and for dm-crypt for example DMA is useless
<wens>
Montjoie: can the crypto engine work without DMA?
<Montjoie>
mripard, if you start working on DMA, please tell me, I greatly look forward on it for enhancing my crypto driver
<wens>
oliv3r: some parts are easier to understand (clocks, pinctrl, gpio), some harder (audio, dma?), but all are a lot of fun
<gzamboni>
mripard, did you got spi without dma working on mainline ?
<Montjoie>
I have asked here several time and nobody seems to know how to get good values for DMA config
<mripard>
Montjoie: hmmm, I worked on SPI without DMA
<Montjoie>
mripard, If you have work on SPI, could you explain me the DMA magic value 0x07070707 used for DMA config please?
<oliv3r>
mripard: ah cool; so DMA will be your next big TODO?
<mripard>
oliv3r: I'm going after SPi as a way to tackle DMA whenever it works
<Montjoie>
arg I need DMA to mainline for my driver
<Montjoie>
oliv3r, you said nobody works to mainline DMA ?
<oliv3r>
wens: but how about this; nobody is working on DMA right now :)
<oliv3r>
wens: i was guessing by that time, DMA might be done too
<wens>
so much for looking at audio, requires dma engine :(
2013-12-04
<Turl>
slapin: it has some dma support I think, at least on one way
<slapin>
Turl: btw, does EMAC on A10 completely poll-based and DMA-unfriendly?
2013-12-03
<Montjoie>
My last major problem is about DMA, I dont understand the config values "wait clock cycle" and "data block size"
2013-12-02
<[7]>
ssvb: regarding that DMA problem, that might be EXPORT_SYMBOL vs. EXPORT_SYMBOL_GPL related, need to check that later
<ssvb>
you also probably need to try enabling dma_buf (based on the messages from your pastebin log)
<oliv3r>
mripard_: i guess your not very enlgihtened about the ahci stack either; since this will need some discussion on the ML anyway, but do you know if our ahci controller has its own dedicated DMA? see https://github.com/oliv3r/linux/blob/0184f6e37fb3ba7641b5edf3ede9477e09f6c5f8/drivers/ata/libahci.c#L573 this change, which obviously isn't multiplatform, but not sure how we'd want to handle that generally other then move it to ahci_enable_dma() and only c
2013-12-01
<montjoie[home]>
same question for source/destination data block size of DMA
<montjoie[home]>
Hello I seek for someone knowing exactly what means "wait clock cycle" for DMA engine of A20 (A20 User manual page 170)
2013-11-29
<focus2>
libv: the 64 bit will outshine a 1gbit ethernet - even with a page turn limit of 10MHz and 8 bytes to a 64bit word, that gives you 80M bytes per second = 1 gbit of data in worst case, but usually if handled by DMA, page change is less frequent and easily get throughputs of 100's of megabytes per second. Easily need 2 x gbit ethernet to handle it.
2013-11-26
<hramrach>
cpu sits there just to program dma for io intensive workloads
2013-11-24
<wens>
either the transmit clock, or DMA setting is wrong
<tomee^>
it's like talking to your DMA controller over a telephone line ;)
2013-11-22
<torbenh3>
mmm... it needs dma engine to work properly, i guess.
<Montjoie>
My last bench with DMA was SS is twice faster as kernel generic AES
2013-11-21
<hglm>
You mean file access is slow? I did notice a programmed I/O vs. DMA option in the Inventra (MUSB) driver -- the default is PIO which is likely to be slow but I don´t whether DMA can work (not tested it).
2013-11-19
<libv>
our headers are not supporting dma_buf yet!
<wens>
arokux, torbenh3: pushed DMA flags in DTS. works if using gmac with u-boot. Gbit might not work, but i can't test that.
<wens>
arokux: i only changed dma parameters for this build.
2013-11-16
<wens>
mripard: dma still needs to be worked out
<wens>
hramrach: then stmmac will output a lot of debug info, including dma descriptors, packet data, etc.
2013-11-15
<oliv3r>
can someone explain to me how it's possible taht some IP has their own dma controller? i mean, the soc has one, how do they 'talk'
<oliv3r>
is it confirmed that the designware mac has it's own DMA controller?
<mnemoc>
but switching to gmac should improve the performance due to the separated dma
<mripard>
and it won't work with dcaches precisely because it uses dma, and does something in the cpu's back :)
<mripard>
hramrach: yeah, from what I looked at, gmac has its own dma controller
<hramrach>
I the mainlining effort page suggests that ethernet uses the main dma controller but that might apply to emac only
<hramrach>
mripard: does it? it depends on HAS_DMA in kconfig but not sure if just selecting that would work
<mripard>
hramrach: doesn't the GMAC have its own DMA controller?
<hramrach>
related to that is anybody working on dma for mainline?
<oliv3r>
hramrach: DMA probablly
<Montjoie>
I just need to track done some random DMA timeout
<Montjoie>
DMA
<arokux>
( wens: the last was dma problem )
<arokux2>
wens: it was the problem in u-boot, phy was visible, but gmac won't work due to dma
<oliv3r>
i don't think we have dma in u-boot do we
<focus>
tobenh3: during file transfer the problems don't appear because DMA is in charge and random page turns are not as frequent
<focus>
arokux: what happens is that the CPUs need to do a lot of jumping and looping - and if that is into the same page, then page turn does not occur - also if big data transfers, then page turn happens only a limited number of times because DMA controller is in charge of the data transfer - so 2 x A20 a lot better communicating through ethernet than direct interprocessor communications
2013-11-07
<montjoie[home]>
its alive!! its alive, DMA finaly work for AES
<Montjoie>
hello, does someone here, is experienced with BIDRECTIONNAL DMA ?