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<leons>
_florent_: thanks so much for integrating my LiteEth timestamping PR!
<leons>
I have one question though (I feel like I'm missing something). You changed the code to make the SRAM Writer only have a result status FIFO when timestamping is enabled
<leons>
I was under the impression by introducing the result status FIFO I was implicitly solving another issue: how does a LiteEth user know how many packets have been sent when not having a result FIFO?
<leons>
Sure, they can count interrupts. Imagine however the OS is pretty busy and it will take a while to do anything reasonable with the interrupt. LiteEth might have sent multiple packets, right?
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<_florent_>
leons: The reasoning is fine and I agree with it, I did this change mostly because it is changing the software API (with CSRs moving) and so would break the current drivers using this API, so I just want to be sure we do it at the right time (and maybe after doing https://github.com/enjoy-digital/litex/issues/548 that could avoid breaking current drivers with the change).
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<leons>
Ah, thanks for the explanation, this makes sense. I already prepared to get my hands dirty in the Linux LiteEth driver to adjust it, but it makes sense that there are many clients relying on it
<leons>
I think it's very important nonetheless, as my driver (without timestamps retrofitted) currently relies on one interrupt routed to the driver per packet, and I'm reasonably sure that caused issues at least a few times already
<leons>
In case one would, in the future, run into the case where the CSR interface is deemed sufficiently broken to need to redesign it backwards-incompatible, wouldn't it make sense to version the interface while we're at it? I'd love to fail fast in my driver if the interface is changed in a backwards-incompatible way. If that might make sense, I'll be sure to add a comment to #548
<zyp>
what you might want to do is add a version register
<leons>
zyp: yup! ideally, always at the start of the CSR bank for each peripheral. An 8-bit number should probably suffice
<zyp>
I've got an upcoming usecase for this too
<zyp>
I've designed an ecp5 based board for the orbuculum project that'll act as a swd/jtag/trace probe: https://bin.jvnv.net/file/e4wot.png
<leons>
zyp: hah, my usecase is "I have a bunch of drivers, and I don't know if updating LiteX will break my drivers in a way that manifests itself in a weird edge-case"
<leons>
I suppose that's a pretty common "usecase" haha
<zyp>
and I'm planning to eventually port the blackmagic probe firmware to run on a vexriscv in the fpga
<zyp>
so it would be nice to be able to present a consistent register interface towards the firmware, since the firmware would be fairly decoupled from the gateware platform
<leons>
zyp: That looks pretty awesome, I didn't know orbuculum yet!
<leons>
Specifically what makes backwards-incompatible changes in CSRs tricky for me is that the OS I'm maintaining the LiteX target for is written in Rust, so I can't integrate it with the usual generated headers
<leons>
And auto-generating the driver's register abstraction from JSON/SVD isn't really a great option either