09:21 <nickoe> Melkhior: Maybe it is because they are just wires and not a register?

12:13 <nickoe> Why does it appear as if the date I get from the LiteDRAMDMAReader when using native port width is garbarage? It works when I set data_widt to 8?

21:18 <nickoe> Ok, I finally made it work, it appears that if I used more than 8 as data width, I need to hold the address for more clock cycles...

21:42 <zyp> were you not looking at the ready signal?

21:59 <nickoe> zyp: mmm, not when changing the address

22:00 <nickoe> zyp: So now I do it like this, https://github.com/nickoe/litex-boards/blob/7ca4099b4b050ea2addecf6e2610a57cf4c757fe/litex_boards/targets/mars_ax3_sim_litex.py#L253-L256

22:01 <nickoe> I am not sure if there is a better way to do it than to assume it will take two cycles :S

22:47 <zyp> okay, I'm not familiar enough with it to tell