lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<mumptai> hi
<mumptai> finally wrapped up the environment to reproduce the bug with empty/trunctuated VCD output
<mumptai> where shall i put/send it?
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<mumptai> sb0, where shall i send the bug-report?
<mumptai> hi gric
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<sb0> mumptai, devel at lists.m-labs.hk
<mumptai> done
<sb0> mumptai, for case 0/1 that's because there's nothing to simulate in case 0 (no simulation function in any module)
<sb0> case 1 adds an (empty) simulation function and makes it work
<sb0> case 2 is not reproducible here; it produces a correct VCD file for me
<mumptai> the tutorial (section 3.2) led me to try case 0
<sb0> hmm I see
<mumptai> yeah, it says something like: add this (...) and you should be waveform
<mumptai> s/be/get/
<mumptai> s/waveform/a waveform/
<sb0> yes, that was written before the new simulation api
<sb0> I'll need to think which should be fixed - tutorial, api, or both
<sb0> for case 2, I should just run simple.py as it is in the tarball and it should produce a broken vcd - right?
<mumptai> actually an empty vcd
<mumptai> (size = 0)
<sb0> it does work for me...
<mumptai> interesting
<mumptai> and no one else had a problem?
<sb0> not as far as I know
<mumptai> okay, i'll have a look if i can trace it back to some issue in my setup
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<sb0> 4.9.0 hopefully has mostly-OK LM32 support
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<sb0> "THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!"
<sb0> (Altera)
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<GitHub116> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/IBmtbw
<GitHub116> migen/master 600ce55 Florent Kermarrec: mibuild/altera_quartus: add support for verilog include
<GitHub60> [migen] sbourdeauducq pushed 2 new commits to master: http://git.io/iRO2ww
<GitHub60> migen/master fef08e8 Florent Kermarrec: mibuild: add bitstream_ext parameter to platforms
<GitHub60> migen/master 82e4980 Florent Kermarrec: mibuild/altera_quartus: set top_level_entity
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