lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<ysionneau> _florent_ hi !
<ysionneau> _florent_: do you have any Cyclon IV DDR2 PHY by chance?
<ysionneau> if yes, I know some OpenRISC guy who would be interested
<_florent_> hi
<_florent_> no I don't have that and I don't have an Altera board with Cyclone IV and DDR2
<_florent_> I'm not very familiar with Atlera primitives, but maybe he can generate the AltMemPhy and do a wrapper for DFI?
<_florent_> (I've only used DDR2 on Altera devices with AltMemPhy)
<_florent_> at least it's less messy than with Xilinx where you get the PHY and the controller with the MIG, here you can generate only the PHY.
<ysionneau> ah cool
<ysionneau> so they give you the source of their PHY(/controller)? (never had a look at that)
<_florent_> not sure, I'm going to check that :)
<_florent_> so you have the sources, but you can simply do a wrapper around the Altera PHY with Migen to provide a similar interface than s6ddrphy
<_florent_> BTW, have you find the issue on the simplesdramcon with DDR?
<_florent_> found sorry
<ysionneau> actually DDR, but no :(
<ysionneau> so far I was simulating my controller (with s6ddrphy) to try to find the issue
<ysionneau> I could just see an issue with dq and dqs being not properly aligned
<ysionneau> today I will simulation lasmicon+s6ddrphy to see how it behaves and try to replicate that on simplesdramcon
<ysionneau> -ion+e
<_florent_> OK, yes it will probably be easier
<ysionneau> would you mind if I copy paste the start of our discussion to Olof (OpenRISC guy I told about)?
<ysionneau> or maybe you prefer I give you his email address so that you can talk to him directly?
<ysionneau> maybe he would be interested in you making a phy for him?
<_florent_> yes you can copy paste and send me his mail address
<ysionneau> ok :)
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<ysionneau> I can now simulate lasmicon, but it seems to never drive the ddr pins ... I guess it is because of the l2 cache
<ysionneau> weird though that my first read do not trigger ddr reads
<_florent_> yes, I remember reducing l2 cache to the minimum when I was doing simulations
<ysionneau> yes I put l2_size = 8 but it still does not drive ddram pins :/
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<_florent_> you can try to hack wishbone2lasmi for that
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<ysionneau> it seems the problem is something else
<ysionneau> cause I've followed the wb2lasmi state machine
<ysionneau> and it goes into refill and gives a strobe pulse to bank0 of bankmachines
* ysionneau still following this path
<ysionneau> maybe it's just a stupid issue from my simulation
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<ysionneau> ah I think I got it
<ysionneau> I think that by default I boot in dfiInjector mode
<ysionneau> so the dfi is controlled by sw and not hw
<ysionneau> I should just initialize the switch to make dfi controlled by hw
<ysionneau> ok good, now ddram pins are driven :)
<ysionneau> ok I can see the same dqs/dq alignment issue, so I guess it's a simulation issue and I need to focus on something else
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<davidc__> ysionneau: I was reading the artiq mailing list, and saw that you guys were having problems flashing papillio-pro boards
<davidc__> ysionneau: I ran across the same issue and may know the solution: the papillio pro board has absolutely terrible SI issues
<davidc__> ysionneau: (at least, boards made from the design files they released do!)
<davidc__> ysionneau: we built a batch at the local hackerspace and all had itermittent flashing issues, which can be mitigated by stitching the ground plane back together
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<davidc__> ysionneau: (ground bounce at the flash IC was measured in volts!)
<ysionneau> ah! interesting!
<ysionneau> what do you mean to actually "stitch the ground plane back together" ?
* ysionneau off to bed