lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub64> [migen] sbourdeauducq pushed 7 new commits to master: http://git.io/xTKY
<GitHub64> migen/master dbdb263 Yann Sionneau: mibuild/kc705: add missing pins on FMC LPC
<GitHub64> migen/master 28c219e Sebastien Bourdeauducq: platforms/kc705: add user SMA clock
<GitHub64> migen/master ba26a40 Sebastien Bourdeauducq: Merge branch 'master' of https://github.com/m-labs/migen
<GitHub167> [misoc] sbourdeauducq pushed 4 new commits to master: http://git.io/xTKO
<GitHub167> misoc/master 8364fe6 Yann Sionneau: target/kc705: allow access to pll_sys signal before BUFG
<GitHub167> misoc/master c9ed38d Robert Jordens: gensoc: missing self.
<GitHub167> misoc/master a3909bb Sebastien Bourdeauducq: Merge branch 'master' of https://github.com/m-labs/misoc
<GitHub84> [artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/xTXw
<GitHub84> artiq/master da917f7 Sebastien Bourdeauducq: initial kc705 support
<GitHub84> artiq/master f855834 Sebastien Bourdeauducq: gui/tools/DictSyncer: remove dead code
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<travis-ci> m-labs/artiq#33 (master - f855834 : Sebastien Bourdeauducq): The build passed.
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<GitHub66> [artiq] sbourdeauducq pushed 5 new commits to master: http://git.io/xke6
<GitHub66> artiq/master 14e481d Sebastien Bourdeauducq: benchmarks: fix imports
<GitHub66> artiq/master ee9d616 Sebastien Bourdeauducq: language/units: add strip_unit function
<GitHub66> artiq/master 61f33a9 Sebastien Bourdeauducq: soc/ad9858: do not put code in __init__.py
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<GitHub148> [migen] enjoy-digital pushed 1 new commit to master: http://git.io/xkIT
<GitHub148> migen/master 54a8a52 Florent Kermarrec: xilinx/programmer: add partial flash_bitstream for vivado (can flash full bitstream, need to be adapted to flash part of the flash (bios, ...))
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<GitHub140> [misoc] enjoy-digital pushed 3 new commits to master: http://git.io/xkBZ
<GitHub140> misoc/master 617bc70 Florent Kermarrec: liteeth: move doc
<GitHub140> misoc/master e4de5a0 Florent Kermarrec: make.py: avoid some actions in make all (do not flash if load-bitstream is specified or if bios is in blockram)
<GitHub140> misoc/master 77a6f58 Florent Kermarrec: gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts
<ysionneau> _florent_ wow, the "vivado scripting language" looks very ... ugly :x
<_florent_> yes... at least for the programmer :)
<ysionneau> for a language invented in 2014 , the syntax is weird :p
<ysionneau> when compared to python/ruby
<_florent_> I'm not sure it's the same team for vivado and the programming tools, because the scripts to run a P&R are not that weird...
<ysionneau> ok
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<larsc> there is a different scripting language?
<ysionneau> or maybe I was not aware of this kind of scripting being available in ISE : https://github.com/m-labs/migen/commit/54a8a52e90a77b43639152fb8eb2847999e6e42f
<larsc> it's all TCL
<ysionneau> ah, I was tempted to say "it looks like tcl"
<larsc> it's like scheme without the braces
<ysionneau> the rare times where I touched tcl was when playing a bit with eggdrops :)
<ysionneau> when*
<larsc> we are scripting all our designs since it makes it possible to easily put the same design onto different carrier boards by putting the common parts into a common file
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<GitHub114> [migen] enjoy-digital pushed 2 new commits to master: http://git.io/xtYm
<GitHub114> migen/master 225a2d4 Florent Kermarrec: report cachesize in wishbone2lasmi
<GitHub114> migen/master e82531c Florent Kermarrec: move dfi/lasmibus/wishbone2lasmi to MiSoC sdram
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<GitHub89> [misoc] enjoy-digital pushed 9 new commits to master: http://git.io/xtYc
<GitHub89> misoc/master b817cf4 Florent Kermarrec: replace self._r_register by self._register in all CSR declaration
<GitHub89> misoc/master 9814001 Florent Kermarrec: create cpu dir and move lm32/mor1kx in it
<GitHub89> misoc/master 9f636f7 Florent Kermarrec: move memtest to sdram
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<GitHub94> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/xtVW
<GitHub94> artiq/master f307897 Sebastien Bourdeauducq: units: fix strip_unit
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<travis-ci> m-labs/artiq#35 (master - f307897 : Sebastien Bourdeauducq): The build failed.
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<GitHub58> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/xt6o
<GitHub58> misoc/master cb38580 Florent Kermarrec: make.py fix indent
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<GitHub190> [misoc] enjoy-digital pushed 2 new commits to master: http://git.io/xqTA
<GitHub190> misoc/master 074f576 Florent Kermarrec: targets: add de0nano (100MHz, integrated bios and SDRAM)
<GitHub190> misoc/master f1200d6 Florent Kermarrec: gensoc: move I/O for rom initialization to make.py
<GitHub177> [misoc] enjoy-digital pushed 1 new commit to master: http://git.io/xqt4
<GitHub177> misoc/master 8e04ef7 Florent Kermarrec: test minicon with de0nano (OK) and fix missing self in gensoc
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<_florent_> LASMICON vs MINICON on the de0nano:
<_florent_> thanks ysionneau :)
<ysionneau> np! It was very interesting to do
<ysionneau> even though it's still not perfect yet, for instance I couldn't make it work with DDR on the M1 board
<ysionneau> but it seems to work fine with SDRAM
<_florent_> it's very interesting for small designs, I wasn't expecting that much
<ysionneau> it's a very very dumb design
<ysionneau> so yes it saves resources, but expect less performance than lasmicon :p
<ysionneau> but I'm glad it's helpful to you :)
<_florent_> yes I know, but when we just want to have some ram it's useful
<_florent_> I'll try to have a look at the DDR next week
<ysionneau> for artiq it was helpful to make it work on papilio_pro which is also small, but to be able to fit as much rtio stuff as possible
<ysionneau> ok thanks!
<_florent_> for the DDR, you were getting completely random data?
<ysionneau> no, not completely
<ysionneau> I don't remember exactly the fail pattern
<ysionneau> but I could see in the memtest some correct data, and some shift
<ysionneau> and definetely some pattern in the fail/success (because there was also some success)
<ysionneau> and some duplicated bytes also
<ysionneau> very weird
<_florent_> hmm OK, I will use LiteScope :)
<ysionneau> I should learn to use it someday
<ysionneau> do you have some nice tutorial for it?
<_florent_> yes you can have a look at the example design
<_florent_> but I want to discuss with sb0 about integrating it directly in MiSoC since LiteEth is now in MiSoC
<_florent_> it will be easier to use it
<ysionneau> good news!
<ysionneau> so basically the file you just linked is a target I can synthesize from MiSoC using make.py -X ?
<_florent_> yes it should work
<_florent_> but I have a make.py directly in LiteScope
<ysionneau> ok
<_florent_> (to create example_designs without MiSoC dependency)
<ysionneau> by default what does it do exactly? Which signal does it dump?
<_florent_> you just have to put the signals you want in self.debug
<_florent_> here it's a simple counter
<ysionneau> oh, very simple indeed
<_florent_> but you can do more interesting things:
<ysionneau> (I meant, seems very simple to use)
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<_florent_> the nice things is that you don't have to handle manually each signal (as you do with Chipscope and SignalTap)
<_florent_> I have to go
<_florent_> have a nice weekend
<ysionneau> you too !
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<GitHub121> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/xmMU
<GitHub121> artiq/master 0127de9 Joe Britton: soc: add_cpu_csr_region -> add_csr_region
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<travis-ci> m-labs/artiq#36 (master - 0127de9 : Joe Britton): The build is still failing.
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