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<rjo>
FelixVi: pretty sure you are wrong. the page size is 256 in the datasheet. and that also seems completely unrelated to any of the symptoms you are seeing.
<rjo>
FelixVi: did you bother checking what i asked you?
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<FelixVi>
rjo, the bin file is fine and it works fine
<FelixVi>
rjo, when you look at the logs I send you, you will see that it's trying to write 2048
<FelixVi>
that could also be the problem, but I didn't want to change things there as I could have messed up other things
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<FelixVi>
In either case, 0x100 fails and 0x20 works, so we have some information about what the problem is
<FelixVi>
I am fine with things working for now, but I'm happy to chase this down if you're interested
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<rjo>
FelixVi: nonsense. look at the code: 2048 = 8*256 is the number of bits in a page and that is what it is writing.
<rjo>
FelixVi: let me be really blunt: given that nobody else seems (in the thousands of different images that we have so far flashed onto the same chip model) to hit your issue, and given that you don't seem to be willing to narrow it down or provide a reproducible test, you won't have anybody else looking into it other than you ;)
<rjo>
i am saying that there is no bug. there might well be one. but from what you do and give there is no way to approach it.
<_florent_>
rjo, cr1901_modern: IIRC one of you wanted to create a wrapper for the SPI core of ARTIQ so that it can be used in MiSoC, have you made some progress on that? (I just wanted to use it to control a AD9154 DAC)
<_florent_>
then once I have something working we could create a test design in your repository that use the jesd204 core
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<rjo>
_florent_: any roadblocks you can see right now? is 4x16b samples per channel at 150 MHz ok?
<rjo>
_florent_: all that will move the the main artiq repo sooner or later anyway. but that should be smooth.
<rjo>
_florent_: currently we are targetting 4x interpolation and 600 MHz data rate, 2.4 GHz dac clock, all four channels independently (none of the IQ data path elements: nco, coarse mod, sinc shaper, phase shifter)
<_florent_>
rjo: I can't say for now for the 4x16b samples per channel, but if that's supposed to be supported by the AD9154, then you can prepare that yes
<rjo>
afaict that's supported
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<rjo>
i just don't know how many gearbox stages and N-times-M-bits-to-K-times-L-bits conversions there are until it dribbles out of the transcievers.
<_florent_>
ok, I'll look at that
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<rjo>
it's ok if you work your way from the transciever side up. just asking if you already had any preference. from my side 4 channels of 4x16 bit at 150 MHz is "natural".
<rjo>
the spi core is copied over from the artiq one (and has been tested there). cr1901_modern is slapping the CSR layer on top of it instead of the wishbone interface for artiq.
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