sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub146> [artiq] sbourdeauducq commented on issue #692: @cjbe Would Oxford fund this? https://github.com/m-labs/artiq/issues/692#issuecomment-316586261
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<GitHub99> [artiq] sbourdeauducq closed issue #777: document replace support on RTIO channels https://github.com/m-labs/artiq/issues/777
<GitHub32> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/d0b21a8e85f75ae1db85c5c889f4d7250143abd8
<GitHub32> artiq/master d0b21a8 Sebastien Bourdeauducq: manual: add short description of drivers, with replace support information. Closes #777
<GitHub44> [artiq] sbourdeauducq opened issue #790: DRTIO switch support for complex Kasli trees https://github.com/m-labs/artiq/issues/790
<GitHub103> [artiq] sbourdeauducq opened issue #791: Wishbone bridge between Sayma AMC and RTM FPGAs https://github.com/m-labs/artiq/issues/791
<Ishan_Bansal> sb0 : Even I try with Array, but the array also do not take Signal as an index.
<Ishan_Bansal> Also array work as an list.
<GitHub103> [artiq] sbourdeauducq closed issue #779: generalizing EEM peripheral interfaces https://github.com/m-labs/artiq/issues/779
<GitHub101> [artiq] sbourdeauducq closed issue #780: ARTIQ interface for KC705 to EEM TTL breakout boards https://github.com/m-labs/artiq/issues/780
<sb0> Ishan_Bansal, the Array is specifically designed to take Signals as indices.
<sb0> look at the example
<bb-m-labs> build #729 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/729
<GitHub155> [artiq] sbourdeauducq commented on issue #563: Let's break the remaining items into separate issues. https://github.com/m-labs/artiq/issues/563#issuecomment-316593257
<GitHub97> [artiq] sbourdeauducq opened issue #792: IOSERDES TTLs for Kintex Ultrascale https://github.com/m-labs/artiq/issues/792
<bb-m-labs> build #533 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/533
<bb-m-labs> build #1630 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1630
<GitHub139> [artiq] sbourdeauducq opened issue #793: 5Gbps/40x DRTIO for Sayma/Metlino https://github.com/m-labs/artiq/issues/793
<GitHub198> [artiq] sbourdeauducq opened issue #794: Clocking, DAC support and JESD synchronization on one Sayma card https://github.com/m-labs/artiq/issues/794
<GitHub44> [artiq] sbourdeauducq opened issue #795: DAC synchronization across Sayma cards https://github.com/m-labs/artiq/issues/795
<GitHub26> [artiq] sbourdeauducq closed issue #563: support kintex ultrascale https://github.com/m-labs/artiq/issues/563
<GitHub98> [artiq] sbourdeauducq commented on issue #563: #794 #793 #792 https://github.com/m-labs/artiq/issues/563#issuecomment-316595191
<GitHub30> [artiq] sbourdeauducq opened issue #796: distributed DMA https://github.com/m-labs/artiq/issues/796
<GitHub171> [artiq] sbourdeauducq opened issue #797: SAWG monitoring and injection https://github.com/m-labs/artiq/issues/797
<GitHub157> [artiq] sbourdeauducq opened issue #798: SAWG on Kintex Ultrascale https://github.com/m-labs/artiq/issues/798
<GitHub139> [artiq] mntng opened issue #799: Minimum SPI clock frequency(equivalently maximum divider) needs documentation https://github.com/m-labs/artiq/issues/799
<sb0> rjo, what exactly is "f,p,a,u modulation by RTIO (eDRTIO) for all interpolators" and "Coherent phase mode (implemented in kernel API and runtime) for frequency/phase updates of the three eDRTIO channels"?
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<rjo> that was explained in the overall design doc that we wrote last year.
<rjo> both were.
<rjo> it started in joe's draft_sayma_metlino_procurement_20160805.pdf
<rjo> mntng: do you feel up to tackling #799 yourself?
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<GitHub168> [artiq] mntng closed issue #799: Minimum SPI clock frequency(equivalently maximum divider) needs documentation https://github.com/m-labs/artiq/issues/799
<GitHub80> [artiq] cjbe commented on issue #692: @sbourdeauducq it might be possible to tack this on to a future contract, else one of us will implement it. https://github.com/m-labs/artiq/issues/692#issuecomment-316639076
<mithro> sb0: Thoughts on https://github.com/SpinalHDL/VexRiscv ?
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<sb0> mithro, haven't tried it, but the author usually does good stuff.
<GitHub132> [artiq] sbourdeauducq reopened issue #799: Minimum SPI clock frequency(equivalently maximum divider) needs documentation https://github.com/m-labs/artiq/issues/799
<sb0> rjo, another gotcha with the SPI implementation is, when you're doing a 8-bit transfer you must do write(0x**000000) instead of simply write(0x**)
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<rjo> sb0: that's extensively documented.
<sb0> it's still a gotcha
<GitHub6> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/189020344c469772445d98fc8cbe02ed72ebc5d0
<GitHub6> artiq/master 1890203 Sebastien Bourdeauducq: spi: fix typo in doc
<GitHub26> [artiq] sbourdeauducq pushed 1 new commit to release-2: https://github.com/m-labs/artiq/commit/0ffc752310451efe48db44517e09d2e482eb691b
<GitHub26> artiq/release-2 0ffc752 Sebastien Bourdeauducq: spi: fix typo in doc
<GitHub196> [artiq] sbourdeauducq commented on issue #799: Alternatively the code could throw an error when the divider values are out of range. https://github.com/m-labs/artiq/issues/799#issuecomment-316720150
<bb-m-labs> build #730 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/730
<rjo> sb0: for those that don't read the documentation?
<rjo> sb0: if that's a gotcha then there are thousands like it in migen/misoc/artiq
<bb-m-labs> build #534 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/534
<bb-m-labs> build #1631 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1631
<mithro> sb0: could that be a candidate for adding risc-v support to MiSoC?
<GitHub132> [artiq] jordens pushed 1 new commit to release-2: https://github.com/m-labs/artiq/commit/0fbacb0002a5ec0df2cd984b8aa7216eba211964
<GitHub132> artiq/release-2 0fbacb0 Robert Jordens: setup.py etc: update license
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<sb0> mithro, dunno. try it :)
<GitHub143> [artiq] jordens opened issue #800: jtag for sayma/ultrascale https://github.com/m-labs/artiq/issues/800
<GitHub55> [artiq] sbourdeauducq commented on issue #800: Are we programming the FTDI chip? I recommend we don't, or only with existing software that is already proven to "work" with their buggy silicon. https://github.com/m-labs/artiq/issues/800#issuecomment-316754706
<GitHub41> [artiq] sbourdeauducq opened issue #801: SAWG external modulation https://github.com/m-labs/artiq/issues/801
<GitHub29> [artiq] jordens commented on issue #800: Right. But IIRC there needs to be some programming to tell the chip how to use and expose the four ports. Maybe that's also something that the manufacturer can do. https://github.com/m-labs/artiq/issues/800#issuecomment-316766184
<GitHub188> [artiq] sbourdeauducq commented on issue #800: Doesn't OpenOCD reconfigure them dynamically? IIRC the only benefits of EEPROM programming are 1) the JTAG port won't appear as a ttyUSB device before OpenOCD claims it 2) fancy USB identifiers. https://github.com/m-labs/artiq/issues/800#issuecomment-316767154
<GitHub138> [artiq] jordens commented on issue #800: IIRC the serial port doesn't appear at all. That needs eeprom programming. Nothing in the current openocd code even touches that. Maybe the JTAG port doesn't need an EEPROM. But that kills one way of distinguishing Saymas. https://github.com/m-labs/artiq/issues/800#issuecomment-316779795
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<cr1901> Would still like to see a full CPU in Migen someday, but that looks like a decent RISCV impl from a quick glance
<GitHub15> [artiq] hartytp commented on issue #778: Thanks @dhslichter and @dleibrandt for the feedback.... https://github.com/m-labs/artiq/issues/778#issuecomment-316855498