sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub175>
[artiq] sbourdeauducq commented on issue #818: @mntng No, ``sys.executable`` cannot be replaced with ``"python"``. There can be multiple Python interpreters available on the system, and on a number of them (e.g. Debian) ``"python"`` refers to Python 2.7, which would break the test.... https://github.com/m-labs/artiq/pull/818#issuecomment-325069729
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<sb0>
_florent_, there shouldn't be ascii-art in __repr__
<sb0>
_florent_, I don't like the get_pads()/GTHPads hack. why not have a list of p/n pairs directly, with those pairs coming from the migen platform system directly (write platform description appropriately)?
<sb0>
I don't see why you had to take clock domain creation out of TransceiverInterface
<sb0>
use_cpll | use_qpll0 -> use_cpll or use_qpll0
<_florent_>
sb0: ok, I'll do the changes
<sb0>
_florent_, thanks
<_florent_>
sb0: but what do you want me to do in the __repr__, remove the ascii-art? should I keep it somewhere else? I'm fine to do what it convenient for you but I need to know what you want :)
<sb0>
_florent_, also I think the priority is to get the bridge to actually work with artiq
<_florent_>
sb0: yes, that's what I'm going to do
<sb0>
__repr__ should be a single-line thing. the ascii-art itself is fine, maybe keep it in source comments?
<_florent_>
sb0: I'll do the others things, can you change the __repr__ while integrating and do what you think is best for you?
<sb0>
ok
<_florent_>
ok thanks
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<sb0>
well. bridge or jesd. both are important
<_florent_>
sb0: I expect to have the bridge working on monday
<_florent_>
sb0: it was working with misoc with my old delay finding procedure
<GitHub96>
[artiq] sbourdeauducq commented on pull request #818 abf3ce8: Are the default values ``description=None, builtin_terminate=False, allow_parallel=False`` not working? If they are working then please use them. https://github.com/m-labs/artiq/pull/818#discussion_r135393304
<rjo>
_florent_: thanks. fyi: the other amc/rtm pair will be with greg again next week.
<rjo>
_florent_: CODEGRPSYNC was always 0x00 in my tests. doesn't that indicate that it fails cgs?
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<wingdu>
some where up ?
<sb0>
wingdu, ?
<forrestv>
why is migen simulation so slow compared to e.g. MyHDL? it seems like i'm getting at least a 10x slowdown with some MyHDL code ported to migen
<sb0>
I guess, because no one optimized the migen simulation and it's as straightforward as it can get
<sb0>
likely doing things like optimizing combinatorial loops/logic will bring about significant improvements
<sb0>
a simple way to speed up the migen simulation is to run it in pypy
<sb0>
maybe you can also look into compiling the comb/sync statements into llvm ir and then running standard llvm optimization passes on them
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<sb0>
_florent_, can you also clean up the bridge user API? (see comments in the artiq/sinara target files)
<GitHub10>
[misoc] sbourdeauducq pushed 3 new commits to master: https://git.io/v53Wr
<GitHub95>
sinara/master b4feedb Greg: simplified schematics & initial version of PCB finished
<sb0>
_florent_, also I think the master core could just keep retrying when init fails
<sb0>
if we want to check that the link is consistently up, we can add a register that is reset to 0 by the CPU and set to 1 whenever the link is restarted
<sb0>
_florent_, and when the link is down and a transaction comes - are you asserting the wb error signal?
<sb0>
_florent_, "need m-labs support to generate csr for rtm in amc header?" << done
<sb0>
_florent_, rjo: is it correct that the hmc830 has active-high CS and hmc7043 has active-low CS?
<sb0>
well. according to the datasheets both are active-low
<sb0>
so why this code: If(hmc_spi_sel,
<sb0>
hmc830_spi_cs.eq(~self.hmc_spi.core.cs_n),
<sb0>
).Else(
<sb0>
hmc7043_spi_cs.eq(self.hmc_spi.core.cs_n)
<sb0>
hmc830_spi_cs.eq(0),
<sb0>
hmc7043_spi_cs.eq(1)
<sb0>
),
<sb0>
maybe this is why the 830 doesn't work?
<GitHub49>
[migen] sbourdeauducq pushed 1 new commit to master: https://git.io/v53B6