<cr1901_modern>
whitequark: You've stared into the conda abyss long enough, perhaps unwillingly. Have you ever seen an issue like this? http://ix.io/1n5I
<whitequark>
cr1901_modern: yes
<whitequark>
thesolution is to not use conda
<whitequark>
you don't have any reason to do so, anyway, unlike m-labs
<cr1901_modern>
I'm not using it willingly :). If it were up to me, I'd find some sort of generic SAT-solver-based package manager for the non-python based stuff, and use pip pointing to a custom package index for the rest.
<cr1901_modern>
(and hope I can get the two to play nice when they interact, like with libboost-python)
<cr1901_modern>
s/SAT-solver-based//
<cr1901_modern>
(Not firing on all cylinders right now)
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<hartytp>
all that is missing is programming the phase shifter during the DAC SYSREF alignment
<hartytp>
however, the DAC doesn't boot up (even without SAWG) and just gives bad CODEGRPSYNCFLG errors
<hartytp>
any ideas?
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<sb0>
hartytp: no idea. didn't joe try 2GHz with interpolation?
<sb0>
er, 1.2
<sb0>
hartytp: are you getting this error with the original artiq code?
<hartytp>
flashing to test that atm.
<hartytp>
could be an issue with the board greg posted me
<hartytp>
ffs
<hartytp>
so, that still happens with current master
<hartytp>
any ideas what could cause that?
<hartytp>
sb0: to check I'm not being silly here: the standalone target needs a 100MHz clock applied to the RTM SMA and nothing else, right?
<sb0>
yes
<hartytp>
well that's borked then
<hartytp>
there is a part of me that is tempted to just cut our losses and spin sayma v2.0 now
<hartytp>
my guess is that a lot of these issues are due to each board having different reworks plus having been around the world 10 times and been a bit chewed up
<hartytp>
and, if every time my board goes into the WUT vortex a different one comes out, it makes tracking issues quite hard
<sb0>
yeah, I don't how many times I told them to be careful about this (and testing...)
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<hartytp>
sigh...
<rjo>
board testing, characterization, history, and each rework need to be tracked and documented end-to-end. it's not magic.
<hartytp>
yes
<sb0>
hartytp: do you know anything about the current board v2 status? I can't get a word from Joe about it
<hartytp>
what about it?
<hartytp>
funding?
<hartytp>
timeline?
<sb0>
yes
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<hartytp>
yes to which? both?
<sb0>
hartytp: yes to both
<sb0>
rjo: how does one get WUT to do that?
<hartytp>
funding, afaict v2.0 hardware is funded
<hartytp>
not sure about software (although, I assume the money is there)
<hartytp>
timeline: asap afacit
<hartytp>
but, I haven't caught up with joe about this for a while
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<sb0>
nothing is funded on software side so far
<hartytp>
well, it doesn't really involve me, but that seems the right approach to me: finish the hardware design first then sort out the software contracts once we know what we're dealing with
<hartytp>
keeps it less open-ended (although, I assume there will be some design contract for you guys, but as I said I haven't talked to joe about that yet)
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<rjo>
sb0: i would send them a log-sheet with the hardware, specify (in the order and in rework shipments) what they are supposed to do, and how they are supposed to track/document it.
<hartytp>
rjo: yes, but even that kind of thing doesn't seem to work
<hartytp>
cf booster. Why did I even bother writing up a detailed specification for the firmware?
<hartytp>
must have asked 10 times "does your firmware match the specification on the wiki?" each time "yes" until I point out that it clearly doesn't
<hartytp>
it's quite frustrating
<rjo>
hartytp: yeah. it's annoying. i see a couple possible things: a) apply the usual fudge factor (2-3 in time and money) b) specify the tests, the setup, ask for a sign off and full report on the measurements/milestones/implementation, say that that's required in the contract/order, c) escalate contractually.
<hartytp>
yes, I got to the point with Booster of threatening to withhold payment
<hartytp>
but, it didn't do much good
<rjo>
maybe a % cut for documented contractual failures works different.
<hartytp>
yes, but Greg already charges well below market rate
<hartytp>
reading between the lines, the reason for that discount is that he's doing it for fun and reserves the right to get distracted on other things that are more fun
<hartytp>
at least that's how I read it
<rjo>
agreed.
<hartytp>
(d) pay the proper rates and use an industrial contractor for any project that's more complicated than an EEM
<hartytp>
but, then, it's not that simple because Greg is *great* at working with physicists to understand what they want
<hartytp>
and also quite good at getting stuck into issues that involve both hw and software
<hartytp>
getting an industrial contractor to do that is also quite tricky
<hartytp>
and, we've had issues with a Keysight contract where they also didn't do what was in the contract and moaned about it endlessly
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<rjo>
yep. i have also seen that from smaller but well known physics companies in funding consortia.
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<_florent_>
hartytp: CODEGRPSYNCFLG error probably means that K28.5s are not received correctly by the DAC (first step of the JESD initialization)
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