sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<mtrbot-ml> [mattermost] <sb10q> @rikstarmans have you tried ClockDomainsRenamer?
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<mtrbot-ml> [mattermost] <rikstarmans> @sb10q that might solve part of my issues; I request the main clock pin so I can pass it as an input to an instance. The platform builder also request this pin when building the module. A pin can't be requested twice and as a result the build fails.
<mtrbot-ml> [mattermost] <rikstarmans> The only solution i see so far is driving an other signal with the main clock using self.sync and then passing this signal to the Instance.
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<mtrbot-ml> [mattermost] <sb10q> well if you want to put the FSM in another clock domain, that's what you should use
<mtrbot-ml> [mattermost] <sb10q> if the FSM and its parent module are all using the same domain only, you can also simply put ClockDomainsRenamer on that parent module
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<mtrbot-ml> [mattermost] <rikstarmans> @sb10q thanks... it does solve the issue of my FSM in another clock domain.
<mtrbot-ml> [mattermost] <rikstarmans> is it possible to infer block rams with migen? I am now thinking of using the block rams on the fpga. it is described in the case of myhdl here http://xess.com/static/media/pages/pygmyhdl/examples/4_blockram/block_ram_party.html
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<mtrbot-ml> [mattermost] <rikstarmans> the problem I have here is don't know how to declare. A 8 bit wide 255 bit deep register in migen. The examples in migen all consider 1 dimensional signal and not reg [ 7:0] mema [255:0];
<mtrbot-ml> [mattermost] <sb10q> use Memory - there's an example
<mtrbot-ml> [mattermost] <rikstarmans> i have used memory... but icestorm doesn't infer block rams from it
<mtrbot-ml> [mattermost] <sb10q> are you using a supported BRAM configuration?
<mtrbot-ml> [mattermost] <rikstarmans> no
<mtrbot-ml> [mattermost] <sb10q> things like async read don't work on many FPGAs (I don't know about ice40)
<mtrbot-ml> [mattermost] <sb10q> and that's a hardware limitation
<mtrbot-ml> [mattermost] <rikstarmans> okay.. so that's why it is not inferring it?
<mtrbot-ml> [mattermost] <sb10q> what do you want it to infer if there's no corresponding hardware?
<mtrbot-ml> [mattermost] <rikstarmans> self.specials.mem = Memory(8, 512, init = 100*[10, 20])
<mtrbot-ml> [mattermost] <rikstarmans> p1 = self.mem.get_port(write_capable=True)
<mtrbot-ml> [mattermost] <rikstarmans> self.specials += p1
<mtrbot-ml> [mattermost] <rikstarmans> self.ios = {p1.adr, p1.dat_w, p1.we}
<mtrbot-ml> [mattermost] <rikstarmans> Results in
<mtrbot-ml> [mattermost] <rikstarmans> nfo: ICESTORM_LC: 1/ 7680 0%
<mtrbot-ml> [mattermost] <rikstarmans> Info: ICESTORM_RAM: 0/ 32 0% <---- THIS SEEMS WRONG
<mtrbot-ml> [mattermost] <rikstarmans> Info: SB_IO: 6/ 256 2%
<mtrbot-ml> [mattermost] <rikstarmans> Info: SB_GB: 0/ 8 0%
<mtrbot-ml> [mattermost] <rikstarmans> Info: ICESTORM_PLL: 0/ 2 0%
<mtrbot-ml> [mattermost] <rikstarmans> Info: SB_WARMBOOT: 0/ 1 0%
<mtrbot-ml> [mattermost] <sb10q> ok, does the generated verilog look unusual? I'm not familiar with icestorm
<mtrbot-ml> [mattermost] <rikstarmans> This is what it looks like:
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] mem[0:511];
<mtrbot-ml> [mattermost] <rikstarmans> reg [8:0] memadr;
<mtrbot-ml> [mattermost] <rikstarmans> always @(posedge sys_clk) begin
<mtrbot-ml> [mattermost] <rikstarmans> if (we)
<mtrbot-ml> [mattermost] <rikstarmans> mem[adr] <= dat_w;
<mtrbot-ml> [mattermost] <rikstarmans> memadr <= adr; <--- THIS LOOKS DIFFERENT
<mtrbot-ml> [mattermost] <rikstarmans> end
<mtrbot-ml> [mattermost] <rikstarmans> This is what triggers inference:
<mtrbot-ml> [mattermost] <rikstarmans> module test(input clk, wen, input [8:0] addr, input [7:0] wdata, output reg [7:0] rdata);
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] mem [0:511];
<mtrbot-ml> [mattermost] <rikstarmans> initial mem[0] = 255;
<mtrbot-ml> [mattermost] <rikstarmans> always @(posedge clk) begin
<mtrbot-ml> [mattermost] <rikstarmans> if (wen) mem[addr] <= wdata;
<mtrbot-ml> [mattermost] <rikstarmans> rdata <= mem[addr];
<mtrbot-ml> [mattermost] <rikstarmans> end
<mtrbot-ml> [mattermost] <rikstarmans> endmodule
<mtrbot-ml> [mattermost] <rikstarmans> ----
<mtrbot-ml> [mattermost] <rikstarmans> So the rdata looks different
<mtrbot-ml> [mattermost] <rikstarmans> This is what it looks like:
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] mem[0:511];
<mtrbot-ml> [mattermost] <rikstarmans> reg [8:0] memadr;
<mtrbot-ml> [mattermost] <rikstarmans> always @(posedge sys_clk) begin
<mtrbot-ml> [mattermost] <rikstarmans> if (we)
<mtrbot-ml> [mattermost] <rikstarmans> mem[adr] <= dat_w;
<mtrbot-ml> [mattermost] <rikstarmans> memadr <= adr; <--- THIS LOOKS DIFFERENT
<mtrbot-ml> [mattermost] <rikstarmans> end
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> This is what triggers inference:
<mtrbot-ml> [mattermost] <rikstarmans> ```
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<mtrbot-ml> [mattermost] <rikstarmans> module test(input clk, wen, input [8:0] addr, input [7:0] wdata, output reg [7:0] rdata);
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] mem [0:511];
<mtrbot-ml> [mattermost] <rikstarmans> initial mem[0] = 255;
<mtrbot-ml> [mattermost] <rikstarmans> always @(posedge clk) begin
<mtrbot-ml> [mattermost] <rikstarmans> if (wen) mem[addr] <= wdata;
<mtrbot-ml> [mattermost] <rikstarmans> rdata <= mem[addr];
<mtrbot-ml> [mattermost] <rikstarmans> end
<mtrbot-ml> [mattermost] <rikstarmans> endmodule
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> So the rdata looks different
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> self.specials.mem = Memory(8, 512, init = 100*[10, 20])
<mtrbot-ml> [mattermost] <rikstarmans> p1 = self.mem.get_port(write_capable=True)
<mtrbot-ml> [mattermost] <rikstarmans> self.specials += p1
<mtrbot-ml> [mattermost] <rikstarmans> self.ios = {p1.adr, p1.dat_w, p1.we}
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> Results in
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> nfo: ICESTORM_LC: 1/ 7680 0%
<mtrbot-ml> [mattermost] <rikstarmans> Info: ICESTORM_RAM: 0/ 32 0% <---- THIS SEEMS WRONG
<mtrbot-ml> [mattermost] <rikstarmans> Info: SB_IO: 6/ 256 2%
<mtrbot-ml> [mattermost] <rikstarmans> Info: SB_GB: 0/ 8 0%
<mtrbot-ml> [mattermost] <rikstarmans> Info: ICESTORM_PLL: 0/ 2 0%
<mtrbot-ml> [mattermost] <rikstarmans> Info: SB_WARMBOOT: 0/ 1 0%
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> This is what the result from migen looks like:
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] mem[0:511];
<mtrbot-ml> [mattermost] <rikstarmans> reg [8:0] memadr;
<mtrbot-ml> [mattermost] <rikstarmans> always @(posedge sys_clk) begin
<mtrbot-ml> [mattermost] <rikstarmans> if (we)
<mtrbot-ml> [mattermost] <rikstarmans> mem[adr] <= dat_w;
<mtrbot-ml> [mattermost] <rikstarmans> memadr <= adr; <--- THIS LOOKS DIFFERENT
<mtrbot-ml> [mattermost] <rikstarmans> end
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> This is what triggers inference:
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> module test(input clk, wen, input [8:0] addr, input [7:0] wdata, output reg [7:0] rdata);
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] mem [0:511];
<mtrbot-ml> [mattermost] <rikstarmans> initial mem[0] = 255;
<mtrbot-ml> [mattermost] <rikstarmans> always @(posedge clk) begin
<mtrbot-ml> [mattermost] <rikstarmans> if (wen) mem[addr] <= wdata;
<mtrbot-ml> [mattermost] <rikstarmans> rdata <= mem[addr];
<mtrbot-ml> [mattermost] <rikstarmans> end
<mtrbot-ml> [mattermost] <rikstarmans> endmodule
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> So the rdata looks different
<mtrbot-ml> [mattermost] <sb10q> okay, you may need to look into the migen source that produces that verilog template
<mtrbot-ml> [mattermost] <sb10q> this may have been fixed in nmigen but afaik not tested
<mtrbot-ml> [mattermost] <rikstarmans> port needs to be defined as p1 = self.mem.get_port(write_capable=True, mode = READ_FIRST)
<mtrbot-ml> [mattermost] <rikstarmans> This results in
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] mem[0:511];
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] memdat;
<mtrbot-ml> [mattermost] <rikstarmans> always @(posedge sys_clk) begin
<mtrbot-ml> [mattermost] <rikstarmans> if (we)
<mtrbot-ml> [mattermost] <rikstarmans> mem[adr] <= dat_w;
<mtrbot-ml> [mattermost] <rikstarmans> memdat <= mem[adr];
<mtrbot-ml> [mattermost] <rikstarmans> end
<mtrbot-ml> [mattermost] <rikstarmans>
<mtrbot-ml> [mattermost] <rikstarmans> assign dat_r = memdat;
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> Memory is still not inferred
<mtrbot-ml> [mattermost] <rikstarmans> port needs to be defined as p1 = self.mem.get_port(write_capable=True, mode = READ_FIRST)
<mtrbot-ml> [mattermost] <rikstarmans> This results in
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] mem[0:511];
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] memdat;
<mtrbot-ml> [mattermost] <rikstarmans> always @(posedge sys_clk) begin
<mtrbot-ml> [mattermost] <rikstarmans> if (we)
<mtrbot-ml> [mattermost] <rikstarmans> mem[adr] <= dat_w;
<mtrbot-ml> [mattermost] <rikstarmans> memdat <= mem[adr];
<mtrbot-ml> [mattermost] <rikstarmans> end
<mtrbot-ml> [mattermost] <rikstarmans>
<mtrbot-ml> [mattermost] <rikstarmans> assign dat_r = memdat;
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> Memory is still not inferred, my guess is that i need to capture it in a module block
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<mtrbot-ml> [mattermost] <rikstarmans> port needs to be defined as p1 = self.mem.get_port(write_capable=True, mode = READ_FIRST)
<mtrbot-ml> [mattermost] <rikstarmans> This results in
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] mem[0:511];
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] memdat;
<mtrbot-ml> [mattermost] <rikstarmans> always @(posedge sys_clk) begin
<mtrbot-ml> [mattermost] <rikstarmans> if (we)
<mtrbot-ml> [mattermost] <rikstarmans> mem[adr] <= dat_w;
<mtrbot-ml> [mattermost] <rikstarmans> memdat <= mem[adr];
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<mtrbot-ml> [mattermost] <rikstarmans> end
<mtrbot-ml> [mattermost] <rikstarmans>
<mtrbot-ml> [mattermost] <rikstarmans> assign dat_r = memdat;
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> Memory is still not inferred, my guess is that i need to capture it in a module block
<mtrbot-ml> [mattermost] <rikstarmans> I guess this is not possible in migen as it does not support hierarchical designs
<mtrbot-ml> [mattermost] <rikstarmans> port needs to be defined as p1 = self.mem.get_port(write_capable=True, mode = READ_FIRST)
<mtrbot-ml> [mattermost] <rikstarmans> This results in
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] mem[0:511];
<mtrbot-ml> [mattermost] <rikstarmans> reg [7:0] memdat;
<mtrbot-ml> [mattermost] <rikstarmans> always @(posedge sys_clk) begin
<mtrbot-ml> [mattermost] <rikstarmans> if (we)
<mtrbot-ml> [mattermost] <rikstarmans> mem[adr] <= dat_w;
<mtrbot-ml> [mattermost] <rikstarmans> memdat <= mem[adr];
<mtrbot-ml> [mattermost] <rikstarmans> end
<mtrbot-ml> [mattermost] <rikstarmans>
<mtrbot-ml> [mattermost] <rikstarmans> assign dat_r = memdat;
<mtrbot-ml> [mattermost] <rikstarmans> ```
<mtrbot-ml> [mattermost] <rikstarmans> Memory is still not inferred, my guess is that i need to capture it in a module block
<mtrbot-ml> [mattermost] <rikstarmans> I guess this is not possible in migen as it does not support hierarchical RTL designs like nmigen
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<whitequark> rikstarmans: please use a pastebin service, your pastes are very disruptive on IRC
<whitequark> regarding your question, you should read yosys logfile, because it explains exactly why it infers or does not infer a BRAM
<whitequark> there is no need to guess
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<Astro-_> @sb10q that issue happens very often to me. I work around it by starting openocd with "ftdi_layout_init 0x20e0 0x3feb" and "ftdi_layout_signal nSRST -data 0x2000" which don't work but cause something like a power-cycling.
<Astro-_> I admin that's not even a hack but sheer luck, hence not committed anywhere.
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<_whitenotifier-5> [nmigen] Fatsie commented on issue #285: Making Instance with clock compatible with EnableInserter - https://git.io/JeN0h
<_whitenotifier-5> [nmigen] whitequark commented on issue #285: Making Instance with clock compatible with EnableInserter - https://git.io/JeNES
<_whitenotifier-5> [nmigen] whitequark commented on issue #285: Add EnableSignal, useful for making Instances compatible with EnableInserter - https://git.io/JeNE7
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