sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<mtrbot-ml_> [mattermost] <pkulik> @sb10q I have one AMC with bitstream that works with 2 RTMs (by works I mean that DACs are recognising that they get sysref signal)
<mtrbot-ml_> [mattermost] <pkulik> (I didn't test with other RTMs yet)
<mtrbot-ml_> [mattermost] <pkulik> I'm now pulling spi flash contents and replicating them to other amc to check if they also work
<mtrbot-ml_> [mattermost] <sb10q> @pkulik does the JESD core work on your boards or do you get "JESD core reported not ready"?
<mtrbot-ml_> [mattermost] <pkulik> on this one AMC:
<mtrbot-ml_> [mattermost] <pkulik> ```
<mtrbot-ml_> [mattermost] <pkulik> [ 8.878456s] INFO(satman::jdcg::jdac): DAC-0 initializing...
<mtrbot-ml_> [mattermost] <pkulik> [ 9.604319s] INFO(satman::jdcg::jdac): ...done
<mtrbot-ml_> [mattermost] <pkulik> [ 9.607628s] INFO(satman::jdcg::jdac): DAC-1 initializing...
<mtrbot-ml_> [mattermost] <pkulik> [ 9.618374s] ERROR(satman::jdcg::jdac): JESD core reported not ready
<mtrbot-ml_> [mattermost] <pkulik> ```
<mtrbot-ml_> [mattermost] <pkulik> so DAC0 yes, DAC1 no
<mtrbot-ml_> [mattermost] <sb10q> it's the exact opposite on mine...
<mtrbot-ml_> [mattermost] <pkulik> btw, do you know why satellite variant without sawg recognizes kasli as drtio master and with sawg (from the same code) it doesn't?
<mtrbot-ml_> [mattermost] <sb10q> no...
<mtrbot-ml_> [mattermost] <sb10q> is this with recent vivado (2019.2)?
<mtrbot-ml_> [mattermost] <sb10q> older vivado has a some GTH bugs
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<mtrbot-ml_> [mattermost] <pkulik> no
<mtrbot-ml_> [mattermost] <pkulik> @sb10q using FPGA SYSREF DDMTD phase target from config: 120
<mtrbot-ml_> [mattermost] <pkulik> how can I delete this value from config?
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<mtrbot-ml_> [mattermost] <sb10q> @pkulik you should upgrade vivado then
<mtrbot-ml_> [mattermost] <sb10q> erase with artiq_flash (flash an empty file into the storage)
<mtrbot-ml_> [mattermost] <sb10q> anyway maybe we should look at sync later, after the other DAC things are working
<mtrbot-ml_> [mattermost] <pkulik> @sb10q Is there a way without clearing flash? I have one "golden" bitstream, which works on one AMC
<mtrbot-ml_> [mattermost] <pkulik> but I didn't identify which of my builds was flashed to this board
<mtrbot-ml_> [mattermost] <pkulik> I have two theories, either it's because this build has awg or I didn't fully recreate my modifications
<mtrbot-ml_> [mattermost] <pkulik> I cloned flash contents to another board so maybe these config values should be different
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<Stormwind_mobile> Is anyone working on (n)Migen or liteX on Intel Max10 FPGAs?
<Stormwind_mobile> Or on icebreaker/ice40 and has a pointer to some kind of tutorial to try out, looking for feedback and possibly improve
<vup> Stormwind_mobile: if you are looking for a general tutorial on nmigen there is this: https://github.com/RobertBaruch/nmigen-tutorial
<mtrbot-ml_> [mattermost] <sb10q> @pkulik clearing the flash storage won't clear the bitstream
<mtrbot-ml_> [mattermost] <pkulik> but it will clear firmware, right?
<mtrbot-ml_> [mattermost] <sb10q> no
<mtrbot-ml_> [mattermost] <sb10q> just use the arguments "storage start" to artiq_flash
<mtrbot-ml_> [mattermost] <pkulik> oh, all right
<Stormwind_mobile> vup: well, I'd love to have some guidance and small, achievable tasks for the beginning. I have a few FPGA boards on my hands, yet I didn't clear the barrier to really get started and going.
<Stormwind_mobile> I played a bit with a fomu in mithro's and xobs's workshop, that's it so far.
<Stormwind_mobile> And that was technically still on the RISC-V level
<vup> Stormwind_mobile: hmm sorry I can't think of any material regarding that offhand (atleast not targeted at (n)migen)
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<_whitenotifier-5> [nmigen] povauboin opened issue #304: ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances - https://git.io/JvJWe
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<_whitenotifier-5> [nmigen-boards] nicolas-robin opened pull request #42: blinky: replace deprecated Signal(max=...) - https://git.io/JvJl5
<_whitenotifier-5> [m-labs/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JvJlb
<_whitenotifier-5> [m-labs/nmigen-boards] nicolas-robin 4f21323 - blinky: replace deprecated Signal(max=...) (#42)
<_whitenotifier-5> [nmigen-boards] whitequark closed pull request #42: blinky: replace deprecated Signal(max=...) - https://git.io/JvJl5
<_whitenotifier-5> [nmigen-boards] whitequark commented on pull request #42: blinky: replace deprecated Signal(max=...) - https://git.io/JvJlN
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<ZirconiumX> wq: If nMigen throws an AssertionError, does that generally indicate a bug with nMigen or my code?
<whitequark> "it depends"
<whitequark> in this case this is a bug in nmigen
<ZirconiumX> Does nMigen check this Switch for completeness?
<whitequark> nope
<whitequark> some other issue, please file an issue with an MCVE
<ZirconiumX> Oh.
<ZirconiumX> I found the issue immediately.
<ZirconiumX> -self.i_piece = Signal(decoder=Piece)
<ZirconiumX> +self.i_piece = Signal(3)
<ZirconiumX> And it elaborates fine
<whitequark> yeah definitely nmigen bug
<whitequark> there's been a few around switches like that
<whitequark> should have been a diagnostic I think
<ZirconiumX> Okay, this is even worse. It appears to be a heisenbug.
<whitequark> huh.
<ZirconiumX> When I hit Ctrl-Z to undo that fix, it now *also* elaborates fine
<whitequark> did I forget an OrderedDict somewhere?
<whitequark> try different PYTHONHASHSEEDs
<ZirconiumX> Seems to break with any PYTHONHASHSEED I try
<whitequark> didn't it just stop breaking?
<ZirconiumX> Yep.
<ZirconiumX> Right
<ZirconiumX> PYTHONHASHSEED=0 python3 testcase.py consistently breaks with Signal(decoder=Piece) and works with Signal(3)
<whitequark> sure, so where's the heisenbug?
<ZirconiumX> That `python3 testcase.py` would only *sometimes* break with Signal(decoder=Piece)
<whitequark> interesting
<whitequark> ok, sure, minimize it with hashseed
<ZirconiumX> Right. This is...odd.
<_whitenotifier-5> [nmigen] ZirconiumX opened issue #305: AssertionError with strange Switch - https://git.io/JvJBi
<ZirconiumX> whitequark: ^
<ZirconiumX> This seems to crash with or without hashseed
<whitequark> great, thanks
<whitequark> I know exactly what the problem is
<ZirconiumX> Do tell
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<whitequark> oh it's just a missing check in dsl.py
<mithro> Stormwind_mobile: you might want to try the nmigen tutorial from https://github.com/RobertBaruch/nmigen-tutorial or the FPGA 101 from _florent_ at https://github.com/litex-hub/fpga_101
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<_whitenotifier-5> [smoltcp] ureeves opened pull request #322: Change mem::uninitialized to mem::MaybeUninit - https://git.io/JvJzT
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<_whitenotifier-5> [smoltcp] Success. The Travis CI build passed - https://travis-ci.org/m-labs/smoltcp/builds/636618297?utm_source=github_status&utm_medium=notification
<_whitenotifier-5> [smoltcp] whitequark commented on pull request #322: Change mem::uninitialized to mem::MaybeUninit - https://git.io/JvJzB
<_whitenotifier-5> [smoltcp] ureeves commented on pull request #322: Change mem::uninitialized to mem::MaybeUninit - https://git.io/JvJgJ
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