<ktemkin>
I like the general (just make all the index pointers wide enough that they won't overflow in the life-age of the universe and then mask off the top of 'em to find the slice you're looking for, and you have a nice async queue that's super readable)
<awygle>
that is elegant indeed, particularly the way it decays to the natural pot ring buffer
<awygle>
(i got to line 74 before i figured out what the difference was)
<whitequark>
ktemkin: the thing is i'm really low on RAM there so i really want NPOT queues
<whitequark>
and i also want addition to be cheap and atomic
<whitequark>
this problem still exists even on cortex-m!
<whitequark>
m3 only gives you 32-bit atomics which are small, and m0 doesn't even have that
<awygle>
especially since all the extra bits are compile-time constants
<awygle>
you pick up a single extra branch
<whitequark>
yep :D
<whitequark>
afaik i'm the first one to publicly document one
<whitequark>
though i guess it should get a lab note or something to make it searchable properly
<awygle>
(or like, a cmov or something i guess)
<awygle>
i wonder if there's an unconditional formulation....
<ktemkin>
(I wasn't suggesting applicability for a use case as much as leading to they're polar opposite types of elegance; but apparently I can't string two sentences together without being distracted)
<ktemkin>
this is the problem with multi-monitor setups sometimes; I can start typing a message about $A and then wind up distracted by reading $A on the other monitor between sentences
<awygle>
truth. i "solved" this by keeping text on my two side monitors small until i need to read it.
<whitequark>
heh
<ktemkin>
part of my problem is that my work area looks like this:
<ktemkin>
it's an infinite collection of distractions
<whitequark>
whoah
<ktemkin>
and everything's off in that picture because I'm sitting across the room on a laptop because I haven't even made my way over there yet today >.>
<awygle>
dang
<awygle>
gah, now i'm branch golfing wq's q
<ktemkin>
oh gods: it's 2020 and I'm considering running an nMigen design on a Cyclone 4; someone bring me to my senses
<whitequark>
hmm, why not cyclone 3? :p
<ktemkin>
cuz I’m only five years late to doing bring up on this lil board:
<ktemkin>
it's kinda cute, despite the weird USB routing
<whitequark>
cute
<ktemkin>
the engineer who in theory assembles our prototypes put one of those on my desk like a year ago and was like "I put all these together years ago and no one ever even touched 'em"
<ktemkin>
(I say in theory because I'm too impatient to give a project to someone else and then -wait- for it to be soldered)
<whitequark>
heh
<awygle>
one of the great joys of the latter half of my 20s has been realizing i don't have to solder shit myself, i can pay somebody to do it for me
<whitequark>
i find microsoldering, especially on ancient, barely laminated PCBs strangely calming
<whitequark>
you have a device from 1998 with a fine pitch QFP and it has no testpoints? that is EXACTLY the thing i love
<awygle>
and i am very glad people who feel that way exist :)
<whitequark>
but i really don't have patience for modern SMT assembly with 0402s
<whitequark>
ironically, i feel like i don't have the hand dexterity, whereas this is clearly not the case based on the above
<_whitenotifier-3>
[nmigen-boards] whitequark commented on pull request #48: Add Alchitry Au board definition - https://git.io/JvcEo
<awygle>
can't debug my internal logic analyzer because my internal logic analyzer is broken :(
<awygle>
do i have to like... set up the clock somehow? that should just be in the board file, right?
<ktemkin>
if the clock domain is automatically created, it's done so with the board's default clock
<ktemkin>
(e.g. if you just use sync without explicitly instantiating a ClockDomain for it)
<ktemkin>
I don't think the ClockSignal is created if you create the clock domain yourself; lemme look
<ktemkin>
yeah, it's done in `create_missing_domain`
<awygle>
persistence of vision is a bitch
<awygle>
my blinky didn't seem to be working, because it's _totally invisible_ until you go up to a timer of at least 21 bits (naturally the example uses.... 20)
<ktemkin>
led going too fast?
<awygle>
like i can't even tell that it's dimmed, which is what i expected
<ktemkin>
lol, yeah
<awygle>
well there goes the "something's wrong with the clock" theory of why this ILA doesn't work
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<_whitenotifier-3>
[nmigen] mszep opened issue #318: pysim: Throw Error or Warning on writing to non-port variable - https://git.io/Jvc6I
<_whitenotifier-3>
[nmigen] whitequark commented on issue #318: pysim: Throw Error or Warning on writing to non-port variable - https://git.io/Jvc63
<_whitenotifier-3>
[nmigen-soc] jfng commented on pull request #7: Add support for extending the address space of a memory map - https://git.io/Jvc1r
<_whitenotifier-3>
[nmigen-soc] whitequark commented on pull request #7: Add support for extending the address space of a memory map - https://git.io/JvcMm
<_whitenotifier-3>
[nmigen-soc] jfng synchronize pull request #7: Add support for extending the address space of a memory map - https://git.io/Jvn3T
<_whitenotifier-3>
[nmigen-soc] codecov[bot] edited a comment on pull request #7: Add support for extending the address space of a memory map - https://git.io/Jvn3L
<_whitenotifier-3>
[nmigen-soc] codecov[bot] edited a comment on pull request #7: Add support for extending the address space of a memory map - https://git.io/Jvn3L
<_whitenotifier-3>
[nmigen-soc] jfng synchronize pull request #7: Add support for extending the address space of a memory map - https://git.io/Jvn3T
<_whitenotifier-3>
[nmigen-soc] codecov[bot] edited a comment on pull request #7: Add support for extending the address space of a memory map - https://git.io/Jvn3L
<_whitenotifier-3>
[nmigen-soc] codecov[bot] edited a comment on pull request #7: Add support for extending the address space of a memory map - https://git.io/Jvn3L
<Sarayan>
is a nmigen sync design supposed to be fully deterministic?
<whitequark>
yes
<Sarayan>
lemme be 100% sure but it looks like my current sim isn't
<whitequark>
if you have one clock domain and no combinatorial loops, then i think every design will be fully deterministic so long as it passes timing
<whitequark>
oh, sim!
<whitequark>
sim should be always deterministic
<whitequark>
even if you have really weird code
<Sarayan>
I may have some other mistakes, so let me be 100% sure
<Sarayan>
ok so, it's a transition timing issue, entirely my fault as far as I can tell
<Sarayan>
cir is col, you can see there's a one sync delay between ca changing and ci3 changing
<Sarayan>
ci3 is col that is
<Sarayan>
pushed the code in that exact state
<Sarayan>
lower down in the log I can actually see that the top bits of ci3 follow ca while the bottom bits, the ones coming from the rom, are delayed by one sync
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<Sarayan>
(feeling like I'm the first external person really shaking cxxrtl. Not a problem, someone has to be it :-)
<whitequark>
Sarayan: try using the "more compatible" code
<Sarayan>
as it happens, I am using it
<Sarayan>
overdrive.p_clk.next = value<1>{1u};
<Sarayan>
overdrive.step();
<Sarayan>
overdrive.p_clk.next = value<1>{0u};
<Sarayan>
overdrive.step();
<whitequark>
hmm
<whitequark>
try -O0
<Sarayan>
since the previous problems, I didn't want to have that being the cause of, well, anything