#nmigen on 2020-05-29 — irc logs at freenode.irclog.whitequark.org

2020-01-27 18:31 ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen

01:08 thinknok has quit [Ping timeout: 256 seconds]

02:56 Degi has quit [Ping timeout: 256 seconds]

02:57 Degi has joined #nmigen

04:19 peeps[zen] has joined #nmigen

04:21 peepsalot has quit [Ping timeout: 246 seconds]

04:51 _whitelogger has joined #nmigen

05:21 _whitelogger has joined #nmigen

05:30 Guest30583 has joined #nmigen

07:24 chipmuenk has joined #nmigen

07:30 thinknok has joined #nmigen

08:43 Asu has joined #nmigen

09:42 <Degi> In a migen FSM, is NextValue(abc, xyz) equal to m.d.sync += abc.eq(xyz) in nmigen?

09:43 <whitequark> correct

10:00 chipmuenk has quit [Quit: chipmuenk]

10:04 <Degi> Thanks!

10:40 cr1901_modern1 has joined #nmigen

10:42 cr1901_modern has quit [Ping timeout: 265 seconds]

10:46 <Degi> How can I change the clock domain of a FSM?

10:50 <whitequark> `with FSM(domain="foo"):`

10:50 <Degi> Thanks, thats neat

13:46 chipmuenk has joined #nmigen

15:38 Guest30583 has quit [Quit: Nettalk6 - www.ntalk.de]

15:47 Guest30583 has joined #nmigen

15:50 Guest30583 has quit [Read error: Connection reset by peer]

16:00 Guest30583 has joined #nmigen

16:31 Guest30583 has quit [Quit: Nettalk6 - www.ntalk.de]

16:34 Guest30583 has joined #nmigen

16:35 peeps[zen] is now known as peepsalot

17:03 thinknok has quit [Ping timeout: 246 seconds]

17:58 cr1901_modern1 has quit [Quit: Leaving.]

17:58 cr1901_modern has joined #nmigen

20:16 electronic_eel has quit [Ping timeout: 240 seconds]

20:17 electronic_eel has joined #nmigen

20:48 electronic_eel_ has joined #nmigen

20:48 electronic_eel has quit [Ping timeout: 264 seconds]

20:52 miek has quit [Quit: miek]

21:06 <Sarayan> In nmigen, is there a selector operator ala m.select(bit, val-if-1, val-if-0) ?

21:07 <vup> Sarayan: Mux

21:08 <Sarayan> cool thanks

21:09 <Sarayan> what's the 0/1 order?

21:09 <Sarayan> not sure where to find a doc

21:10 <vup> Mux(sel, val-if-1, val-if-0)

21:11 <vup> https://github.com/nmigen/nmigen/blob/master/nmigen/hdl/ast.py#L712-L727

21:11 <Sarayan> oh indeed, in the source

21:11 <Sarayan> thanks

21:18 Guest30583 has quit [Quit: Nettalk6 - www.ntalk.de]

21:49 thinknok has joined #nmigen

22:07 chipmuenk has quit [Quit: chipmuenk]

22:12 Asuu has joined #nmigen

22:13 Asu has quit [Ping timeout: 256 seconds]

23:42 <_whitenotifier-c> [nmigen] shawnanastasio opened issue #393: Signal decoder inference for Enums doesn't work for Layout members - https://git.io/JfKgr