ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting TBD
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<_whitenotifier> [nmigen] hansfbaier commented on issue #554: Strange simulator behavior: clock signal pausing while sync blocks are speeding up - https://git.io/JtLaH
<_whitenotifier> [nmigen] hansfbaier edited a comment on issue #554: Strange simulator behavior: clock signal pausing while sync blocks are speeding up - https://git.io/JtLaH
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<_whitenotifier> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JtLVz
<_whitenotifier> [YoWASP/yosys] whitequark ddd26ed - Update dependencies.
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<_whitenotifier> [nmigen-boards] shenki opened pull request #137: Add iCE40-feather - https://git.io/JttlD
<_whitenotifier> [nmigen-boards] shenki commented on pull request #137: Add iCE40-feather - https://git.io/Jttl9
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<_whitenotifier> [nmigen-boards] joshajohnson commented on pull request #137: Add iCE40-feather - https://git.io/Jtt4Q
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<_whitenotifier> [nmigen-boards] whatnick commented on pull request #137: Add iCE40-feather - https://git.io/JttdI
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<tcal> I _think_ I'm seeing an issue with comparison and signedness -- I have a Signal(32) compared with literal "0". It seems the generated Verilog performs an unsigned comparison (which I what I'd expect), while nMigen simulation does a signed comparison. I didn't see any filed issues similar to this. Has anyone noticed anything like this? I'll work on paring my design down to a small case...
<whitequark> that could be a bug in one of several components, please do file a bug with an MCVE
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<_whitenotifier> [nmigen-boards] shenki commented on pull request #137: Add iCE40-feather - https://git.io/JtqTd
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