#nmigen on 2021-03-30 — irc logs at freenode.irclog.whitequark.org

2021-02-27 05:40 whitequark[m] changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://freenode.irclog.whitequark.org/nmigen

00:29 <_whitenotifier-5> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JY8yv

00:29 <_whitenotifier-5> [YoWASP/nextpnr] whitequark 297c0c4 - Update dependencies.

00:57 <_whitenotifier-5> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JY8Hy

00:57 <_whitenotifier-5> [YoWASP/yosys] whitequark 360e75a - Update dependencies.

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07:30 <anuejn> fdsa: I tried the same thing yesterday

07:30 <anuejn> you can find my WIP code here: https://github.com/anuejn/nAmp/blob/master/gateware/liteeth_nmigen.py

07:31 <anuejn> disclaimer: it does not work (but neither does the litex code when used directly)

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15:44 <d1b2> <twam> Thanks. That worked well!

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16:46 <sensille> can i add a process to sim which does not keep the simulation from terminating? i want to have one main process that drives the simulation, and a few helper processes

16:47 <whitequark[m]> you can add a passive process

16:47 <whitequark[m]> `yield Passive()`

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16:53 <sensille> works, thanks

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22:59 <fdsa> anuejn: That's exactly the structure I was after, thanks! Interesting project, here's two links you might find interesting: FIR filters in nmigen, and a bunch of other dsp stuff

22:59 <fdsa> https://comparch-resources.ece.gatech.edu/labs/intro/intro/

22:59 <fdsa> https://harmoninstruments.com/blog/

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