<gatecat>
should hopefully have clocks and FFs working in the next few days and then blinky, and then hopefully not much further to attosoc!
<gatecat>
also if anyone knows a better way of programming RBFs without Quartus than sitting as an RNDIS gadget and flinging them over ssh, then I'm all ears
<Sarayan>
nice
<Sarayan>
you'll need pll too, I'm starting to understand things about them though
<gatecat>
for blinky?
<Sarayan>
for attosoc
<gatecat>
fabric clock divider should be good enough to start with
<gatecat>
in any case, attosoc might meet timing at 50MHz even without timing driven PnR
<Sarayan>
true, you do have enough information to get the clock input to anywhere you want at this point, which is rather cool
<Sarayan>
is the cmuhg doc understandable btw?
<Sarayan>
the other cmux are going to be similar if it's ok
<gatecat>
yeah, it should be enough to get a basic clock routed which is the main thing
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<Sarayan>
it got much clearer once I got the schematic down
<gatecat>
the other thing that'd be really great to document at some point is the mlab & m10k pin mappings for their different modes; and how the config bits should be set as well
<Sarayan>
I suspect m10k is more interesting than mlab at the start
<gatecat>
yeah, that seems reasonable
<Sarayan>
note that for mlab, m10k and friends there is no information that I have that is not in mistral
<Sarayan>
iow, we're going to have to do fimwares with a specific config, and see how it looks like through decomp
<gatecat>
so I think the main thing I need for those is the mapping from cell pins to pnode (which I suspect varies depending on width mode, etc)
<gatecat>
yeah, that will probably have to be traced
<Sarayan>
somebody has to do it :-)
<gatecat>
it might be worth making a tool that can trace these pin mappings; based on routing to fixed IO or location locked DFFs
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<Sarayan>
I think routes2 does some route resolution alreadu
<Sarayan>
I think routes2 does some route resolution already
<Sarayan>
or maybe it's routes without a 2
<gatecat>
yeah, it does, and it's been very useful already :)
<gatecat>
the remaining part is the bit that sets up the constrained pins/dffs and does the tracing
<gatecat>
*correlates the traced routes
<Sarayan>
yeah
<Sarayan>
we probably could whip up some python for that
<gatecat>
indeed
<Sarayan>
tbh, the most annoying part is building a list of pins we can use :-)
<Sarayan>
and an example verilog of whatever with an explicit instancing we can connect to the pins
<Sarayan>
it's very much in my todo list but I put the priority on what other people couldn't easily do
<gatecat>
sure, that's very reasonable
<gatecat>
I need to nerdsnipe you into adding Arria 10 support too, so I can use those cards I bought :p
<gatecat>
(dw I've got plenty of work to do scaling up nextpnr's performance first...)
<Lofty>
gatecat: I believe trabucayre has support for Cyclone V in openocd?
<gatecat>
you mean openFPGALoader?
<Lofty>
Yeah
<gatecat>
it looks like it needs an svf file, and I don't think we have a tool to generate those yet
<Sarayan>
gatecat: Depends, are you going to pay to get me a quartus pro license?
<Sarayan>
There is no non-paying quartus for arria10 afaict
<Lofty>
Sarayan: no, but we could ask rombik_su nicely.
<gatecat>
ah excellent, the readme only mentions svf
<Sarayan>
and given buying an arrai10 board in the first place is fucking expensive, I'm not that attracted
<Lofty>
Sarayan: can I twist your arm into Cyclone 10 GX instead for my obnoxiously expensive dev board
<Lofty>
(that one *is* free)
<Sarayan>
Lofty: quartus pro has as extra compressed/encrypted perhaps-xml stuff in addition to the ddb that describes the configurations of the blocks that's real annoying
<Lofty>
Well, failing that, we already have the databases for Arria V, somewhere
<Sarayan>
tbh, I'd love to solve timings before I go in-depth in qpro
<Lofty>
Mhm
<Lofty>
That I can help with ^.^
<Sarayan>
mostly I'm trying to trace how quartus_sta works on a toy project
<Sarayan>
It's fucking complicated
<Lofty>
Sarayan: I think you're looking at that wrong
<Lofty>
As we understand it, STA uses the spice models, right?
<Lofty>
For routing it's impractical to actually use SPICE for timing
<Sarayan>
mostly yeah
<Lofty>
So they've probably got a database of timings somewhere already
<Sarayan>
oh, they do
<Lofty>
That's what we need :P
<Sarayan>
find out of the get quartus_fit to dump per-step timings and I'll get you the db
<Sarayan>
how
<Sarayan>
at that point I can only do that with sta
<Sarayan>
find a way to get something better that maximum usable clock out of fit and sure, I'll avoid spice
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<Lofty>
Well, it's interesting to note you can call the quartus_sta functions from quartus_fit
<Sarayan>
the dmf files are the within-block timings, the fdi files are the routing timings (both are seriously annoying to use mind you), when spice is activated it also uses the ddb_cyclonev_*_model.ddb files with have the internal block descriptions (they're hell)
<Sarayan>
so if you can get timing outputs *without* the model files being used (you can check that with PDB_ASCII_DUMP) you win
<Sarayan>
a normal run of fit doesn't use the model files
<Sarayan>
only dmf and fdi
<gatecat>
must admit I'd be really curious to see what the spice models looked like
<gatecat>
although given they contain probably quite detailed and proprietary process information, might be best not to make too much noise about them either
<Sarayan>
mwahahaha no
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<Sarayan>
they contain a connection network, r*c measurements, distances, and probably some driving power info
<gatecat>
no transistors?
<Sarayan>
didn't look like it much
<gatecat>
that sounds more like the model Xilinx use (drive strengths, Rs and Cs)
<gatecat>
I'd barely call that SPICE
<gatecat>
afaik that's kinda the model VPR uses too
<Lofty>
There might be a reason for that :P
<Sarayan>
but I'm not 100% certain, because I'm nowhere near understanding everything yet
<Sarayan>
really feels like that though
<Lofty>
Now to try to remember the magical PDB_DUMP_ASCII invocation