02:06 <whitequark> ha, using verilog to go straight to layout, skipping schematic capture

02:06 <whitequark> I like this: https://twitter.com/azonenberg/status/645412545637969920 http://redmine.drawersteak.com/projects/achd-soc/repository/entry/trunk/boards/hdl-components/power/LTC3374.v

02:43 <DocScrutinizer05> errr, ohwell

02:49 <DocScrutinizer05> I prefer drawing schematics to writing code for generating netlists

02:52 <whitequark> writing code would save you so much repeated work

02:53 <whitequark> you can support typical design for an entire family of parts with the same code

02:53 <whitequark> no more forgetting to update something, no more diffs of XML garbage, etc

03:31 <DocScrutinizer05> hmm?

03:32 <DocScrutinizer05> I hardly ever do repeated work

03:33 <DocScrutinizer05> there's a thing called c&p, in e.g. eagle-7 there are even modules that can be as complex as you want and nested arbitrarily deep, and you use them like a chip or any other component in any level of the module hierarchy

03:34 <DocScrutinizer05> and I think odds are I forget something in a verilog "net plan" while in a schematics it's pretty obvious when some wire is missing

03:50 <DocScrutinizer05> prolly a matter of personal preferences

10:11 <larsc> not bad

15:39 <kristianpaul> not bad indeed

20:07 <qwebirc15330> Hello

20:08 <qwebirc15330> My god ram is a complicated world

20:08 <qwebirc15330> I just figured out that most of ram I bought in the past are 100% crap, overclocked above specs by manufacturer

20:09 <qwebirc15330> Both from G-Skill and Kingston

20:09 <qwebirc15330> I didn't even knew this was a thing

23:00 <wpwrak> i guess the ability of combining graphical and textual circuit descriptions would be nice. there are many things where a drawing is much clearer than any "program" would be. but then there are also cases where doing things graphically is just unnecessary torture.