<azonenberg>
Current layout update. Everything in the signal path up to and including the gain block (plus the secondary gain channel) is done
<azonenberg>
MCU subsystem at bottom, plenty of free space there
<azonenberg>
bottom right corner blob is the DAC, final placement uncertain still
<azonenberg>
middle right is the output stage, not yet placed
<azonenberg>
then top is power supply
<azonenberg>
Tentative thought is to shove the mcu subsystem into the bottom left, dac into bottom right, maybe some of the LDOs and voltage references
<azonenberg>
then remaining power along the top
<azonenberg>
total board depth will be 75 mm or less, i think we should have no problem fitting in the 25x75 target area i was aiming for. Even 25x50 for the AFE could be doable
<azonenberg>
leaving plenty of space on the back of a 100mm wide acquisition board for the ADC
<azonenberg>
The current layout is also bulky because of the strap resistors on the ADL5205, all of those pins will just be tied straight to power/ground once i verify this config is good
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<azonenberg>
hmmm i think in the next AFE i should move the antialiasing filter after at least the offset stage
<azonenberg>
the bessel-thomson LC filer has high return loss in the stopband
<azonenberg>
filter*
<azonenberg>
So incident RF energy >100 MHz on the probe connector will be reflected which i'm not thrilled about
<azonenberg>
for the characterization board i'll keep it, but since the actual adc+afe board is a new layout anyway i think i'll move it there
<_whitenotifier-3>
[starshipraider] azonenberg pushed 1 commit to master [+0/-0/±4] https://git.io/JvQSa
<_whitenotifier-3>
[starshipraider] azonenberg 0cd1f32 - Continued entry-afe-characterization layout
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<_whitenotifier-3>
[starshipraider] azonenberg pushed 1 commit to master [+0/-0/±1] https://git.io/JvQ90
<_whitenotifier-3>
[starshipraider] azonenberg e1266d3 - Finished initial layout of MCU/DAC area
<electronic_eel>
azonenberg: if you want to move the aa filter - why not invest the extra hour redoing the layout of that part and have it in this board?
<electronic_eel>
if there are some problems with the position of the filter, you want to find out about it as soon as possible. saves you another board respin
<azonenberg>
it would involve a filter redesign too
<azonenberg>
the current filter is single ended, as is the attenuator
<azonenberg>
more importantly i want to see if it actually causes problems
<electronic_eel>
for example when you put it behind the offset stage, it'll be differential. could add some asymmetries
<electronic_eel>
ok, so this idea is not "I'll move it in the next rev" but more "if we see some return loss problems, I'll move"
<azonenberg>
Yeah
<azonenberg>
we'll need to design a new filter for the 250/350/500 MHz scopes anyway, and maybe make some other tweaks to the AFE
<azonenberg>
so i will probably make a new characterization board with a differential filter on that one
<azonenberg>
after the offset stage
<azonenberg>
There's going to have to be testing of other stuff anyway at that point, like a proper comparator based trigger with TDC
<_whitenotifier-3>
[starshipraider] azonenberg pushed 1 commit to master [+0/-0/±2] https://git.io/JvQ5K
<_whitenotifier-3>
[starshipraider] azonenberg 0c63749 - Added test point to 1V8 rail. Layout for 1V8 and 3V3 rails.
<Degi>
azonenberg: Why not put the filter before the ADC instead of right at the beginning?
<Degi>
Nvm you literally said that one comment above. Should have read the logs first...
<Degi>
Anyways if active probes are properly terminated, the return loss shouldn't be a problem
<Degi>
Nice layout ^^
<Degi>
The unplaced components floating off the side look kinda funny
<Degi>
Hmm couldn't you just put the single ended filter on each wire of the diff pair?
<Degi>
I really like the group delayof the filter. 4.4 ns to 100 MHz...
<Degi>
Maybe we could test the AFE with the input filter bridged over, then we can see to how many MHz we can use the same design.
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<Degi>
azonenberg: As long as you switch P/N twice, it should be fine
<Degi>
Even if you switch once, we can just add a - in software
<Degi>
Huh I simulated that filter and at 100 MHz assuming a probe with 50 ohm output impedance, you get 4.7 dB more voltage at the input node than at low frequencies. But the output from the filter is fine. I think active probe drivers should be internally terminated with 50 ohm to not reflect the reflections.
<Degi>
Hm a differential filter with 2% value mismatch between the lines (one has 2% more on everything) seems to not worsen the step response by much.
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<Degi>
Maybe a signal generator (at least a digital one) could be useful, for example you could use the scope to read out a SPI chip or a CCD sensor.
<Degi>
I mean if we already have a logic analyzer, we could have a logic generator too
<electronic_eel>
that is what the glasgow is for - it can't just be used as la, but to interact with lot's of digital stuff, so it can be spi master, i2c master and so on
<Degi>
Hm reading out CCDs requires digital and analog
<electronic_eel>
there is quite a bit of engineering necessary to make outputting stuff save, like level shifters and so on
<electronic_eel>
you could sync glasgow and a scope, there is a a sync in/out on glasgow for this kind of stuff
<Degi>
Neat
<awygle>
Everybody is so psyched about Glasgow lol. It's kind of surreal to me
<Degi>
Hm isnt making outputs save easier than making inputs safe?
<Degi>
Maybe for the future we could design a DAC board in the same form factor as the ADCs. That way you could have 4 channel DAC and 4 channel ADC and use that to characterize parts (hysteresis curves, power loss in transformers. S parameters, etc...)
<electronic_eel>
Degi: making outputs safe is much harder than inputs
<Degi>
Because of short circuits etc?
<electronic_eel>
with an input you can just use a voltage divider and a comparator
<electronic_eel>
with outputs you can't put a strong resistor in series, otherwise the signal going out would be attenuated too strong
<electronic_eel>
for example lvc cmos can usually drive >20mA
<Degi>
I mean if somebody ties an output to some high voltage, I guess that's kinda their problem? But I think there are a bunch of ICs that are short circuit resistant
<Degi>
Well you could use ESD protection diodes and fuses probably
<electronic_eel>
if somebody ties an output to some high voltage, your neat scope is toast
<Degi>
I mean you can isolate the level shifter from the FPGA
<electronic_eel>
you want your testgear to be at least somewhat resilent
<electronic_eel>
also there are a lot of protocols which change the signal direction based on protocol, like qspi, swd,...
<Degi>
Hm isolated level shifters and a TVS diode on the power rail...
<electronic_eel>
if you get your protocol decoding wrong, you create a short. the circuit should survive this
<Degi>
I thought of stuff like reading out a CCD (because we have analog channels) tbh
<Degi>
Yes but from like 5 V or what your logic rail is or GND...
<electronic_eel>
don't get me wrong, it is of course possible to do. but it is not that easy either. I would declare it being out of scope for a scope
<electronic_eel>
better create some good interface, like external trigger in/out, to hook in other instruments designed exactly for that
<Degi>
Hm okay
<Degi>
Would a DAC card make sense?
<electronic_eel>
a dac card would have to be followed by some analog output stage (with filters, offset, output protection)
<electronic_eel>
then it would be a proper arb gen
<electronic_eel>
that would make sense to have
<Degi>
We could probably just reverse what we currently have? I think our OP amp is even short circuit resistant
<electronic_eel>
but I don't know if it needs to be directly within the scope. if the arb is a separate instrument which can be accessed from within the same software, and then be synced with trigger in/out, osc ref in/out, I think that would be enough
<electronic_eel>
somewhat fast arb gens are usually dds, so they need a strong filter on the output. also they usually provide much more power (like +- 5V into 50 ohms)
<electronic_eel>
so I'd say the analog section is completely different
<electronic_eel>
but I might be wrong at that
<Degi>
Well we do have a filter and an OP amp capable of 80 mA which is like +- 4 V
<Degi>
Like half the price of the HMCAD if you consider it per channel
<electronic_eel>
yes, they are affordable. I have one of them
<electronic_eel>
they are quite nice, but they also have some quirks. like when you change the waveform parameters on the go by turning the knob, you sometimes get glitches
<Degi>
I meant the DAC price not the siglent thing... lets check that
<electronic_eel>
I ack that this isn't an easy problem to fix, but it can get really annoying in practice
<Degi>
Hm I guess changing voltage requires changing relais? That probably glitches
<electronic_eel>
not always, I think there are like 2 voltage ranges. the relay is only needed when changing between these ranges
<Degi>
Hm is it the digital input data that glitches? That could probably be fixed tbh
<electronic_eel>
it is more like changing pwm duty or frequency
<Degi>
Hm weird
<electronic_eel>
yes, it is the digital data. they generate one waveform, then the new one with the new parameters. you have to calc the correct position to change over
<Degi>
I mean if you do PWM it shouldn't be too hard to do it glitch free?
<electronic_eel>
yeah, but pwm is not all this thing can do. you have tons of arb waveforms and can modulate them on top of each other and so on
<electronic_eel>
and at a certain point it gets complicated to calc the correct change from one waveform to the other
<Degi>
Like a sinewave with a triangle wave frequency sweep. That could be somewhat complicated to make the frequency changes continuous when the direction switches.
<electronic_eel>
I'm certain it could be fixed, but I understand why they didn't fix it for all cases
<Degi>
I kinda wonder what siglent uses to get 20 Vp-p at 500 MHz
<electronic_eel>
it is not 20vpp at 500mhz. it is 1.28Vpp above 350mhz and into HiZ, that is 0.64Vpp into 50R
<Degi>
Oh hm
<electronic_eel>
would be more of a power amp than a arb gen otherwise...
<Degi>
Well the OP amp I linked there could probably do 17.5 Vp-p into 50 ohm at nearly 200 MHz, above that it drops down
<Degi>
Oh oops more like 10 V lol.
<electronic_eel>
often the linearity, intermodulation and speed drop down when go somwhere near the limits, so you won't do that for a test instrument where you want a quality signal
<Degi>
Hm I think it should be able to do 10 Vp-p at 350 MHz, not sure how linear it would be but that is within output current and slew rate specs...
<electronic_eel>
the question is if you just want some signal at this power or a high quality, clean signal you can rely on. when it is just the first, why not just stick a power amp after a low-power arb gen?
<Degi>
Hm yeah you could probably do that
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<azonenberg>
electronic_eel: i do plan to build a signal generator at some point. But that's a later project
<azonenberg>
as far as bidirectional ios, that's the problem i had with starshipraider
<azonenberg>
Making a 1.2-5V LVCMOS I/O cell tolerant to +/- 12V in fault conditions is extremely difficult
<azonenberg>
starshipraider basically is targeting the same goal as glasgow but with ethernet, no partial reconfig, all of the protocols in fpga all the time with a runtime adjustable crossbar
<azonenberg>
it's been on hold while i focus on analog stuff lately
<azonenberg>
well we can build prototypes of both designs and compare them :)
<electronic_eel>
yes, that would be fun
<electronic_eel>
when I have worked on my circuit a bit more, it would also be nice if you could do some si testing on it, you got better equipment than I for this sort of thing
<azonenberg>
Sure
<azonenberg>
Btw, the other problem with starshipraider's io is getting high enough io speeds at wide range
<azonenberg>
my design requires two different io drives depending on the vccio level with muxing between them
<azonenberg>
because the level shifter that's fast enough at 1.2V isn't 5V vcc tolerant
<azonenberg>
and the 5V one is too slow below about 2.5
<electronic_eel>
yes, that will be an issue at these kind of speeds
<azonenberg>
That io board is going to probably be a six layer, extremely dense design
<electronic_eel>
but I think 5v cmos is not common on real high speed stuff
<azonenberg>
my oshpark prototype is full of uDFNs and WLCSPs and the vias are bigger than the ics
<azonenberg>
and fast 5V isnt really necessary
<azonenberg>
but fast LVCMOS18, and true 5V output for talking to old TTL stuff, is
<azonenberg>
when you have that, the 5V gets fast kinda automatically
<azonenberg>
again the challenge comes from making this a kitchen sink io cell instead of specializing it
<electronic_eel>
do you have switchable pullups/pulldowns like glasgow too?
<azonenberg>
Yes
<electronic_eel>
at full fpga speed?
<azonenberg>
Yeah analog muxes between the resistor and signal path
<electronic_eel>
ok, kitchen sink ;)
<azonenberg>
The PCB is going to be crazy. i had something like four analog muxes and two wlcsp level shifters per channel
<azonenberg>
times eight channels
<azonenberg>
and probably HDI filled via in pad
<azonenberg>
i've only prototyped 2 channels on oshpark and need to respin that with some bug fixes
<azonenberg>
but the full board will be "iphone motherboard" level packing of 0201s and WLCSPs
<electronic_eel>
but 8 ch will get tight fast
<azonenberg>
with a QSH-030 to the mainboard on one side and a QTH-030 on the other side for connecting to the probe card connector (fanout to sma, mmcx, or whatever io du jour you want)
<electronic_eel>
16ch of this seems more usable
<azonenberg>
no you misunderstand :)
<azonenberg>
the oshpark prototype host board only has one io bank on it
<azonenberg>
the full starshipraider will be 6 layers, with 10G instead of 1g ethernet
<electronic_eel>
ah, how many banks do you have planned for the final board?
<azonenberg>
a sodimm of ddr3 instead of hyperram as storage
<azonenberg>
and four 8-bit banks
<azonenberg>
each with their own vccio and input threshold
<electronic_eel>
ah, ok that's more like it
<azonenberg>
oh thats another thing, inputs are comparator based with dac driven thresholds
<azonenberg>
vccio tracks a dac reference
<azonenberg>
and there's an ADC on each bank for monitoring an external vccio, you can choose to use or ignore it
<azonenberg>
so you can say "drive outputs at lvcmos33 with 1.0v threshold"
<azonenberg>
or "drive outputs at ext vcc with 0.5*vcc threshold"
<azonenberg>
like i said kitchen sink :)
<electronic_eel>
hehe, don't you think that you went a bit overboard with that design ;)
<azonenberg>
it's meant for, among other things, solving the problem i have as a hardware pentester of going onsite with a client and not having the dongle i need
<azonenberg>
so i want ALL the dongles
<azonenberg>
LA, jtag, uart, gpio, or arbitrary custom protocol at whatever voltage the hardware i've never seen before uses
<azonenberg>
voltage, or voltages
<azonenberg>
the idea is to throw a starshipraider, power brick, and a bunch of probes in a pelican case and know i'm set no matter what the hardware looks like
<electronic_eel>
I'd add a scope and at least basic soldering equipment
<azonenberg>
well that's where this scope comes in :p it's a lot more portable for field use
<azonenberg>
and i have yet to come up with a field soldering kit but lain has a decent one i might borrow some ideas from
<azonenberg>
i have had to solder 0.5mm tqfp with a non temp controlled iron, a helping-hands magnifier, and unidentifiable flux i bought in the back room of a store on apliu street in hong kong
<azonenberg>
not an experience i'd like to repeat
<electronic_eel>
I have seen some people rage about these litte chinese usb powered soldering irons
<azonenberg>
she's got one of those
<azonenberg>
its apparently halfway decent
<miek>
another argument for putting USB-PD on the scope! :D
<azonenberg>
you need a laptop to run the UI anyway
<azonenberg>
lol
<azonenberg>
but yes this scope will be far more packable than a big tall scope with an lcd on it
<azonenberg>
especially if you take the rack ears off
<monochroma>
"why isn't this working!?! ...wait this isn't my active probe... this is my soldering iron!"
<miek>
passive probe, active probe, melty probe...
<electronic_eel>
lol
<azonenberg>
lol
<azonenberg>
melty probe
<azonenberg>
sma attached soldering iron
<monochroma>
XD
<azonenberg>
just crank the DDS up all the way
<azonenberg>
tune it to 13.56 MHz
<miek>
hah
<azonenberg>
and slap a metcal tip on the end of the coax
<electronic_eel>
ok, now I know why Degi wanted a high power function gen
<azonenberg>
lol
<azonenberg>
i mean think about it
<azonenberg>
the dut has to be off when you're soldering
<azonenberg>
why keep the awg on? :p
* azonenberg
goes off to get breakfast before he gets any other terrible ideas
<awygle>
it's 2pm azonenberg
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<azonenberg>
awygle: yes, and i was working until 4am on the afe test board
<azonenberg>
i've left the house twice in the past month, can you blame me for having a totally whacko sleep schedule? :p
<awygle>
yes because neither have i :p
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<electronic_eel>
come on, it is sunday. can't blame anyone for sleeping in on sunday
<azonenberg>
electronic_eel: in grad school after i finished taking classes and was largely doing research, i had no real reason to be anywhere - or even awake - at a specific time
<azonenberg>
so my body gradually shifted onto its natural schedule
<azonenberg>
20 hours awake, 8 asleep, six days a week
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<azonenberg>
if this quarantine/lockdown keeps up much longer i expect to end up on that
<electronic_eel>
I'm usually working better in the evening/late evening than in the morning. but with growing age this begins to not work out so well and I get headaches if staying up too long