<azonenberg>
does that make more sense WRT being able to see the pings?
<azonenberg>
you can see 14 bytes of TLP header which aren't parsed yet because this is a link layer decode
<azonenberg>
followed by what looks like 10 bytes of header data being written to the chip (looks like 4 bytes of data and 6 zero padding bytes)
<azonenberg>
and then the start of the frame
<azonenberg>
then each subsequent TLP in the packet has the 14 byte TLP header only and then frame content
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<monochroma>
ah, yeah :D
<azonenberg>
keep in mind there are multiple layers of encapsulation
<azonenberg>
this is not a pcie ethernet dongle
<azonenberg>
it's a pcie *usb* dongle
<azonenberg>
pcie usb controller*
<azonenberg>
With a usb ethernet dongle plugged into it
<azonenberg>
So i'd have to back out two levels of encapsulation to actually see ethernet frames
<monochroma>
lol yeah
<azonenberg>
that would be a really cool demo of glscopeclient's analysis pipeline capability though
<azonenberg>
there's nothing out there that can decode ethernet frames inside usb traffic inside pcie traffic lol
<azonenberg>
but since the pcie usb decoder will just output usb frames, you'll get the same result as if you had applied the usb-ethernet decode to a usb decode captured off the wire there
<azonenberg>
the beauty of strongly typed filter graph architectures :D
<azonenberg>
anyway that's a long ways out
<azonenberg>
first step is TLP parsing
<azonenberg>
then i will probably work on glitch filtering the usb 1.x stack
<azonenberg>
somebody on twitter sent me some waveforms they were trying to decode
<azonenberg>
looks like when the slew rate is too low from a long cable my decoder sees false SE1 states
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<_whitenotifier-f>
[scopehal-apps] azonenberg pushed 2 commits to master [+0/-0/±3] https://git.io/JkrMT
<_whitenotifier-f>
[scopehal-apps] azonenberg 7c86bca - PCIe gen2 RX mask: added max voltage limits