azonenberg changed the topic of #scopehal to: libscopehal, libscopeprotocols, and glscopeclient development and testing | https://github.com/azonenberg/scopehal-apps | Logs: https://freenode.irclog.whitequark.org/scopehal
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<azonenberg> I guess a good next step would be trying to gpu accelerate rendering of protocol decode text
<azonenberg> well not textr
<azonenberg> but the little blobs around the text
<azonenberg> the colored outlines
<azonenberg> if you're zoomed out on an 8b10b trace or similar i suspect there's a lot of cairo time wasted rendering it
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<_whitenotifier> [starshipraider] azonenberg pushed 2 commits to master [+10/-0/±2] https://git.io/JLDNa
<_whitenotifier> [starshipraider] azonenberg bed8ee0 - Updated AKL-PD1 design with SMPM
<_whitenotifier> [starshipraider] azonenberg 83a2429 - Added full board AKL-PT2 sim (incomplete)
<_whitenotifier> [scopehal-apps] azonenberg opened issue #305: GPU accelerated rendering of protocol decode event bubbles - https://git.io/JLDxk
<_whitenotifier> [scopehal-apps] azonenberg labeled issue #305: GPU accelerated rendering of protocol decode event bubbles - https://git.io/JLDxk
<_whitenotifier> [scopehal-apps] azonenberg labeled issue #305: GPU accelerated rendering of protocol decode event bubbles - https://git.io/JLDxk
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<azonenberg> SI verification of MEAD logic pod at 1.25 Gbps including cable losses. This is what you would see at the input to MAXWELL, with another about 0.6-0.7 dB of loss from the OSHPark host board
<azonenberg> Which is to say, this is about what the eye would look like all the way from probe to FPGA on an average length trace on MAXWELL
<azonenberg> The longest trace, channel 1, will have about another 0.6 dB of loss past what you see here
<azonenberg> The vertical eye opening here is about 200 mV and a kintex-7 IBUFDS is specced to go down to 100 mV differential. So I think we have a fair bit of margin
<azonenberg> Hmmmm
<azonenberg> actually there's plenty of vertical margin but horizontal margin is less good. Since we're doing async oversampling rather than hardware CDR you need at least two samples in the eye opening to get data recover
<azonenberg> So this is a little iffy
<azonenberg> Also threw together a quick and dirty diffprobe design
<azonenberg> schematic done, need to do a little review on it then start layout
<azonenberg> this is a naked diff amplifier board, takes +/- 2.5V on a pair of barrel jacks
<azonenberg> no regulation, no offset calibration
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<_whitenotifier> [starshipraider] azonenberg pushed 1 commit to master [+4/-0/±0] https://git.io/JLyn2
<_whitenotifier> [starshipraider] azonenberg db6c808 - Initial AKL-AD1 schematic (no design review yet)