00:24 <azonenberg> So this is lovely

00:24 <azonenberg> Trying to figure out how to deskew my LA and analog channels on the lecroy driver correctly

00:24 <azonenberg> it seems the LA board has its own RTC separate from the scope

00:24 <azonenberg> And it's currently *14 seconds* fast

00:25 <azonenberg> so trigger times are all out of whack

00:25 <azonenberg> yet somehow the scope has some other way to figure out timing because analog waveforms on the display reliably show ~100ns offset from digital

00:27 <azonenberg> oho

00:27 <azonenberg> The HorStart flag seems to be what I need

00:57 <_whitenotifier-5> [scopehal] azonenberg pushed 2 commits to master [+2/-0/±11] https://git.io/JYAFm

00:57 <_whitenotifier-5> [scopehal] azonenberg b7ee8e7 - LeCroyOscilloscope: parse <HorStart> tag in digital waveforms to correctly display skew between analog and digital channels. Fixes #404.

00:57 <_whitenotifier-5> [scopehal] azonenberg 793895b - Initial implementation of DDR1 command bus protocol decode

00:57 <_whitenotifier-5> [scopehal] azonenberg closed issue #404: LeCroy: digital and analog channels displayed out of sync with each other - https://git.io/JYAC7

01:07 <_whitenotifier-5> [scopehal-docs] azonenberg pushed 2 commits to master [+0/-0/±2] https://git.io/JYAbF

01:07 <_whitenotifier-5> [scopehal-docs] azonenberg 6648ff0 - Initial documentation of Pico driver

01:07 <_whitenotifier-5> [scopehal-docs] azonenberg 8c7859a - Added heading for DDR1 command bus protocol decode. Added brief intro text for DDR3 and de-embed filters, but not full docs.

01:08 <_whitenotifier-5> [scopehal-apps] azonenberg pushed 3 commits to master [+0/-0/±4] https://git.io/JYANY

01:08 <_whitenotifier-5> [scopehal-apps] azonenberg bb3b775 - Updated submodules

01:08 <_whitenotifier-5> [scopehal-apps] azonenberg 2b431a9 - HistoryWindow: when saving waveform metadata, correctly handle negative trigger phase values

01:08 <_whitenotifier-5> [scopehal-apps] azonenberg 04173e7 - OscilloscopeWindow: load trigger phase values with full 64 bit integer precision

01:09 <azonenberg> https://www.antikernel.net/temp/IMG_20210406_183235.jpg playing around with the DDR1 protocol decode on an old linksys router

01:10 <azonenberg> https://www.antikernel.net/temp/ddr1-1.png

01:10 <azonenberg> https://www.antikernel.net/temp/ddr1-3.png

01:37 <azonenberg> And now fighting opencl de-embeds giving incorrect results

15:38 <Degi> Whats the max voltage on the 16 GHz channels?

16:48 <azonenberg> Degi: 5V or... I think 2V? depending on the v/div setting

16:48 <azonenberg> probably an attenuator gets switched out

16:56 <Degi> Is it like very ESD sensitive?

17:04 <azonenberg> i mean, any high speed test equipment is going to be

17:04 <azonenberg> although there's a 50 ohm termination at the input which i imagine provides some level of protection

17:04 <azonenberg> vs a high-z input

17:05 <azonenberg> But i've never had any history of esd problems in my lab thanks to the grounded floor

17:05 <azonenberg> it's not like, say, a GMR HDD head where 50V of ESD will kill it

17:06 <Degi> Hm, I mean like a 20 V pulse which is a few nanoseconds long

17:09 <azonenberg> I mean, i wouldn't want to find out but there's probably clamp diodes that would handle that