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<awygle>
Where can I find the documentation for clk2ff or dff2clk or whatever it's called? Is that a Yosys pass?
<ZipCPU>
I think so .... check the yosys doc's ... it should be within there.
<awygle>
Ah OK it's clk2fflogic
<awygle>
Which is a pass, and replaces clocks with derivatives of the global clock
<awygle>
Presumably this is for verifying multi clock designs?
<ZipCPU>
Actually, I think it's the opposite.
<awygle>
How so?
<ZipCPU>
I think clk2fflogic gets rid of the clock entirely, and replaces all clocked logic with the internally generated $global_clock.
<ZipCPU>
The problem then, though, is that you'll watch your logic within your VCD files change ... without the clock line changing.
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<awygle>
Well, yes. But surely the only reason to do such a thing is for formal verification of cross-clock designs.
<awygle>
For unclocked designs there's nothing to remove, and for single clock designs there's no need to change anything
<ZipCPU>
Look at it this way ... I've often gone through some hoops to create a simulated i_clk, such as assuming that it changes on every $global_clock, etc.
<ZipCPU>
If you set opt2fflogic, IIRC, you don't need to do that at all--it just ignores the clock wire.
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<awygle>
Ah, I see. I'll have to try that out
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