clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<awygle> well, the _proof_ of my UART receiver goes _very_ quickly. the cover unfortunately....
<awygle> oh wow, yices is hilariously faster
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<awygle> final score, Z3 took 0:56:28 and yices took 0:00:51
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<awygle> success! all invalid input is rejected, all valid input is accepted! and it's not even midnight yet ;)
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<promach> awygle: your UART passed induction check ?
<awygle> promach: well, the receiver did. And I want to add more features. Currently the input must be within 0.6% of the nominal baud rate which is not ideal.
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<awygle> Happy to discuss more tomorrow, or you can wait for the blog post. Tonight it is well past time for sleep.
<promach> awygle: what blog post ?
<promach> input must be within 0.6% of the nominal baud rate which is not ideal. ?
<promach> awgyle: did you push your UART coding to any public github ?
<promach> I am working on verifying UART as well, but I am stuck in induction "forever"
* awygle zzzzzzzzzzzz ask me in twelve hours zzzzzzzzzz
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<ZipCPU|Laptop> awygle: I have yet to use "live" in sby
<ZipCPU|Laptop> sorear: My puzzle was the issue of detecting stack overflow, then dumping the register set to memory. That just seems quite problematic to me. Perhaps its common across all stack machines, but from my humble estimation it seems to destroy all of the benefits of the stack windows in the first place.
<ZipCPU|Laptop> awygle: For SymbiYosys, don't forget to add the "-f" flag to the command line, or you will run into directory reuse problems.
<ZipCPU|Laptop> sorear: Well, there's that an the issue of how you assign processes to processors, although I suppose that might not be any worse than on any (other) SMP machine.
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* awygle yawns, stretches
<awygle> Okay, I'm awake and open for business
<awygle> promach: you can find my current work at https://github.com/awygle/spirit/tree/uart_lite_wip
<awygle> like i said, there's quite a bit that i want to change, but it does pass induction, bmc, and (crucially) over
<awygle> *cover
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<awygle> ZipCPU: turns out cover properties are important
<awygle> last night i created a very nice uart receiver that just never accepted any input
<awygle> so, of course, it happily breezed through induction and BMC
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<Exaeta> can I have multiple outputs feed into the same input without or gates?
<Exaeta> basically, I want to have many outputs, where only one will trigger at a time
<awygle> Exaeta: that's either a wire OR or a one-hot mux depending on how you implement it. it's done but it's potentially dangerous. also I'm not sure how to code it in Verilog.
<awygle> Exaeta: for general questions like that maybe check out ##fpga, it's generally more active
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<promach_> hi awygle
<awygle> hi promach_
<promach_> did you push your UART code to some github ?
<awygle> yes, it's in the logs here
<awygle> it's just the receiver and i want to do a fair amount of revision, but it rejects all invalid input and accepts all valid input
<promach_> fair amount of revision ?
<promach_> I do not get what you are trying to convey
<awygle> i want to eliminate bit_recovery and pull its functionality into character_recovery
<awygle> i also want to switch to sampling the center of the bit instead of requiring a bit to be exactly the correct number of bit times (allows for a larger clock skew)