clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<sammylin> @ZipCPU, I'm here in regards to your AXI-Lite demo slave
<ZipCPU> Good evening, sammylin!
<ZipCPU> You must live in a different time zone ;)
<ZipCPU> Do you use AXI-lite much?
<sammylin> I'm EDT
<sammylin> I use it occasionally. It's more of a curiosity thing than anything else.
<ZipCPU> Ok
<ZipCPU> Have you ever used or looked at Vivado's demo version?
<ZipCPU> i.e. what you get when you ask Vivado to create a piece of AXI-lite IP for you?
<sammylin> I think I've done that before, but I don't recall if I ever went to production with it.
<ZipCPU> Sure
<sammylin> I'm assuming they spit out Verilog or VHDL depending on the target language set in Vivado?
<ZipCPU> Yes, exactly
<ZipCPU> My problem is that I don't normally use AXI much at all, much less AXI-lite. That leaves me in a poor position to test whether a piece of code such as this might work.
<ZipCPU> While I've built a set of AXI-lite properties, that's still different from actually running something on hardware.
<ZipCPU> Would you be willing to help me out with that at all? The core is pretty simple.
<sammylin> Shirley, I can try. ;)
<ZipCPU> See PM then
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