clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<azonenberg> ZirconiumX: down the road i want to build a 2-way superscalar, hyperthreaded rv32i core to see how fast i can push it
<azonenberg> in-order though, i'm not trying to be BOOM
<azonenberg> i also want to try to build something tiny and size optimized a la picorv32, maybe even start with the picorv32 design, but hand tune it with RPMs to try and squeeze the max clock rate and least area i can out of it
<ZirconiumX> azonenberg: I think there's potential in a very wide in-order core, akin to what Nvidia are trying with Carmel.
<azonenberg> So, i have another design that isnt riscv based that i want to get back to
<ZirconiumX> I presume you've heard of SERV
<azonenberg> it's 3 IPC VLIW but all instructions are ternary and the pipeline is Y-shaped
<azonenberg> specifically meant for cryptographic code
<azonenberg> no integers, possibly not even arbitrary branching
<azonenberg> it's meant to be a black box sitting between a tcp/ip stack and application layer, or similar
<azonenberg> but trying to be agile enough that you can load new algorithms in the future rather than being tied to e.g. AES
<azonenberg> and with guaranteed single cycle execution of all instruction, no caches, no timing side channels
<azonenberg> dedicated rom/ram for instructions, memory mapped fifo for tx/rx data, constant storage/sbox rom, and scratchpad for temporary state
<azonenberg> Basically there's three ALUs that each do r32 op r32 op imm32
<azonenberg> except the third one operates on the output of the first two, instead of registers
<azonenberg> so you only need one regfile write port despite doing 3 or 5 IPC (depending on if you count a ternary operation as one or two "instructions")
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<ZirconiumX> CPU architecture is a very interesting thing
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<azonenberg_mobil> interesting indeed
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<trmm> back on the LPF versus parameters in the verilog; which one wins? if the LPF has a drive strength or slew rate, can the verilog override it?
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<ZirconiumX> Right, I *believe* I have a live value table implementation
<ZirconiumX> Or at least part of one
<ZirconiumX> Is it preferable to use symbiyosys or yosys-smtbmc?
<ZirconiumX> (maybe a question for ZipCPU)
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<ZipCPU> SymbiYosys
<ZipCPU> It's much simpler than yosys-smtbmc, gives you access to more solvers, and handles formats and format conversions for you
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<maikmerten> my HX8K dev board keeps growing wings: https://pasteboard.co/IkMO5UO.jpg
<tpb> Title: Pasteboard - Uploaded Image (at pasteboard.co)
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* ZirconiumX sighs
<ZirconiumX> I really don't understand formal methods
<ZirconiumX> I've read a lot of articles on it
<ZirconiumX> But I just don't 'get' it
<ZirconiumX> I can't even prove that after reset my program counter points to the reset address
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<ZirconiumX> pepijndevos: you ever looked at bit-serial architecture?
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