clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<develonepi3> Hello All On a Raspbian GNU/Linux 9 (stretch) I have a working nextpnr-ice40 ver 7d5dba3. I upgraded to Raspbian GNU/Linux 10 (buster). The versions of gcc version 6.3.0 (stretch) gcc version 8.3.0 (buster). My ver of nextpnr-ice40 compiles and runs on my RPi3B+ (buster). It does not create the catzip.asc & catzip.bin files. My nextpnr-ice40 fails at iteration 200. My arachne-pnr (buster) does create catzip.asc & catzip.bin files. Thanks in
<develonepi3> advance. Any help is appreciated.
<ZirconiumX> What do you want help *with?*
<ZirconiumX> That nextpnr does not converge?
<develonepi3> Yes it gets to 4 nets and 43 arcs and fails. I am running with -f at present time. 4 nets 8 arcs.
<daveshah> What design is it? How utilised is the FPGA? Have you seen if a different seed will work?
<tnt> just how full is that design ?
<develonepi3> It is HX8K running a zipcpu on cat-board with sdram 72%. I have not tried a different seed. What should I use for arg --seed arg?
<ZipCPU> If it's working, then leave the seed argument off
<daveshah> It's not working
<daveshah> Just try values from 2 upwards for --seed
<ZipCPU> Are you using nextpnr?
* ZipCPU reads history
<develonepi3> Yes nextpnr-ice40 failed at iteration 200 did not meet 4OMHz with -f option.
<tnt> develonepi3: did you try HeAP ?
<tnt> --placer heap
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<develonepi3> I tried to upgrade nextpnr adding eigen3-dev it would not compile I --placer heap must be a new option.
<ZipCPU> Did you try building nextpnr with "make -j1" (after the cmake command)
<ZipCPU> ... that is, to build the updated nextpnr?
<develonepi3> Yes it would fail about 10%
<develonepi3> Anything greater than 1 locks the RPi.
<ZipCPU> How much RAM does your RPi have?
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<ZirconiumX> It's a 3B+, so 1GB
<develonepi3> My Pi is just a 1G waiting to get my Pi4 with 4G
<ZipCPU> That'd be tight. How about creating a large swap device? So whatever doesn't fit in memory gets swapped to disk?
<ZipCPU> There are network options for off board storage if necessary. It might end up being slower than molasses, but is should still work
<develonepi3> I already did that 100 to 1000 swap since that was need to build bare metal (FPC & Lazarus) software for the Pi
<ZirconiumX> ZipCPU: faster than pitch, though!
<develonepi3> I don't think it is a memory issue since on 73.9 swap is used 648.1 free. from
<develonepi3> 1000
<tnt> No one packacked nextpnr yet ? (with builds on ARM)
<develonepi3> The ver nextpnr-ice40 on buster 205442812 is bigger stetch 195635244 I guess since all the boost packages were bumped up 1.62 to 1.67.
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<develonepi3> Hello all made a mistake MiB Swap: 1000.0 total, 927.6 free, 72.4 used. 644.2 avail Mem
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<develonepi3> Hello All: I was able to get a catzip.bin on (buster) raspbian RPi3B+ with nextpnr-ice40 --seed 8 --freq 40 --hx8k --pcf $(PCFFILE) --json catzip.json --asc catzip.asc in the Makefile pi@mypi3-1:~/testbuilds/tb/catzip/sw/host $ ./arm-wbregs version 0800010 ( VERSION) : [....] 20190709 which is the correct result. Thanks
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<f003brv> Hello
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<f003brv> Is anyone else having trouble using iceprog on newer Mac OSX?
<f003brv> It works fine on my older Mac
<ZirconiumX> f003brv: define "trouble"
<f003brv> Sure, i get this error: Can't find iCE FTDI USB device (vendor_id 0x0403, device_id 0x6010 or 0x6014).
<f003brv> despite following this: http://www.clifford.at/icestorm/notes_osx.html
<tpb> Title: Project IceStorm Notes for Installing on OSX (at www.clifford.at)
<f003brv> doing kentunload for com.apple.driver.AppleUSBFTDI driver does not fix
<f003brv> tpb: thanks tried it already and works fine on my older Mac as mentioned
<adamgreig> should nextpnr use the lut carry-outs properly on ice40? my 64bit adder is kinda slow and the critical path is the entire carry chain from 0 to 63
<adamgreig> not sure if anything can be done
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<f003brv> just checked with lsusb and I see the device too
<f003brv> is there a support email
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<pepijndevos_> Does yosys have any useful passes to go from a sea of muxes to more insightful logic?
<pepijndevos_> I used icebox_vlog to convert a bitstream to verilog, and now trying to make that a bit easier to look at.
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<daveshah> You might find that `abc` without any arguments gets you something a bit more useful
<daveshah> (this will remap to a default set of gates)
<daveshah> might need a `techmap; opt` first if it is in `$mux` rather than `$_MUX_` cells
<adamgreig> is there a convenient way to stick a signal into a black box that stops it being optimised away, besides setting it to a port?
<daveshah> adding `(* keep *)` might help
<adamgreig> thanks, i'll have a go
<pepijndevos_> will try
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<pepijndevos_> yea, now it has a bunch of actual logic gates... 415 of them
<pepijndevos_> (also needed a proc)
<adamgreig> are you doing that ice40 ctf by any chance?
<pepijndevos_> yea haha
<adamgreig> enjoy :p
<adamgreig> i just went from the default icebox_vlog mux output by hand manually
<adamgreig> it was a bit tiresome...
<pepijndevos_> A BIT??
<adamgreig> once you get the pattern most of them are the same
<adamgreig> just have like six notebook pages filled with https://photos.app.goo.gl/u8f8AMse1eJ7Pm727
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<pepijndevos_> ehhhh, not sure if I'm that dedicated. I was mainly interested in the bitstream part, which turned out pretty trivial because, you know... icestorm.
<pepijndevos_> Love the notebook though
<adamgreig> there are easier, smarter ways i think
<pepijndevos_> looking at graphiz is probably not it though https://twitter.com/pepijndevos/status/1148687966593851392
<adamgreig> hah
<adamgreig> yea that is not super duper informative
<daveshah> I wonder if cover would be useful here
<pepijndevos_> Does that do some sort of reachability/testability analysis?
<daveshah> Yes
<tpb> Title: SymbiYosys/cover.sby at master · YosysHQ/SymbiYosys · GitHub (at github.com)
<daveshah> This won't help if the bitstream contains any excessively difficult cryptographic functions though
<pepijndevos_> Might try tomorrow. Not really going to learn much about reverse-engineering FPGAs, but learning more Yosys internals can't hurt either.
<adamgreig> i definitely considered just running the verilog in a simulator and fuzzing it :P
<pepijndevos_> Right... but that basically means brute-forcing an 8-char password in a simulator, right?
<adamgreig> you might like to hope a smart fuzzer would figure it out quicker, but in this case i don't think it actually would
<adamgreig> doing it by hand wasn't too bad though, really
<pepijndevos_> Looking at that ball of wires, it does not seem to be a simple shift register that compares with the password. I'm guessing some sort of hash function, but maybe I underestimate the explosive growth of low level logic.
<pepijndevos_> Cover seems fun to try.
<daveshah> You might need to try and find the UART clock divider and patch it out for cover to complete quickly enough
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<pepijndevos_> If the "challenge" is "look at this code with a notebook in hand" I think I'll find something else to do.
<adamgreig> fwiw that is not the nominal challenge
<adamgreig> you can turn the muxes into four-input boolean expressions pretty quickly by hand though
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