<whitequark>
Sarayan: if you are directly poking posedge_p_clk it will not apply to you
<Sarayan>
wq: I wasn't, there was too many caveats, so I'm using the slow, safe version
<whitequark>
what it does mean is that some designs that would previously converge in >1 delta cycle for no good reason, now always converge in 1 delta cycle
<whitequark>
ah
<whitequark>
then it very much may apply to you
<whitequark>
I am slowly getting to the point where those caveats may be automatically checked
<Sarayan>
I know that my designs can be fully converged in one delta cycle
<Sarayan>
up to this point at least
<whitequark>
how many do they currently take?
<Sarayan>
Dunno. Suspect one, I do nothing weird
<whitequark>
three, if you don't do anything weird
<Sarayan>
ok
<whitequark>
one to propagate the clock pulse, one to propagate the *results* of the posedge, one to determine that the design converged
<Sarayan>
:-)
<Sarayan>
fuck, need to recompile yosys
<Sarayan>
yosys: error while loading shared libraries: libffi.so.6: cannot open shared object file: No such file or directory
<whitequark>
in theory, this can be reduced to just one, while remainign fully safe
<whitequark>
the patch i mentioned on twitter makes it always 3
<whitequark>
instead of "usually 3 but sometimes *far* more"
<Sarayan>
urgh, I have slang in there, compile takes even longer
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<Sarayan>
argh, the interface changed
<whitequark>
of what?
<Sarayan>
main.cc:371:3: error: use of undeclared identifier 'value'
<Sarayan>
main.cc:183:1: error: use of undeclared identifier 'cxxrtl_design'
<Sarayan>
I guess I must be missing a namespace or something
<whitequark>
oh
<whitequark>
what -I flag do you use?
<Sarayan>
wait, I have bigger isues
<whitequark>
it should be -I <yosys-root> or -I /usr/local/share/yosys
<Sarayan>
yosys.cmd went wrong
<whitequark>
without the backends/cxxrtl/...
<Sarayan>
I had an empty c++ file generated for some reason
<whitequark>
h
<whitequark>
*ah
<whitequark>
btw, you can use separate compilation now
<whitequark>
-b 'cxxrtl -header' -o design.cc makes design.cc + design.h
<Sarayan>
oh, interesting
<whitequark>
so you don't have to spend time recompiling your stuff
<Sarayan>
I still have to recompile my stuff given the header changes
<Sarayan>
or at least pretends to
<whitequark>
that's true; I can make it so that it won't update the .cc or .h file if it is about to write the exact same thing inside
<whitequark>
hm, not the .cc file, but for the .h file, I can
<Sarayan>
doesn't the header have to change as soon as the internal state layout changes anyway?
<whitequark>
Sarayan: actually, if your design converges in 1 delta cycle, the header only contains registers
<whitequark>
ie sync signals
<Sarayan>
ok, my step sizes vary between 2 and 5
<whitequark>
yes, then you'll benefit from the PR I am about to send
<Sarayan>
cool
<whitequark>
btw, can you show me your driver code again?