clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<Forty-Bot> why is /r/yosys submission restricted?
<Lofty> Given the only mod on there is Claire, she probably doesn't want to deal with it
<Forty-Bot> why not get more mods?
<Forty-Bot> or at least pin a post saying why it's closed
<Lofty> Claire's not here
<Lofty> So, the question is kinda pointless
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<ZipCPU> It's restricted? I wasn't aware of that
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<Forty-Bot> ZipCPU: yeah, I only noticed because I thought it was fishy that there had been no posts for 2 months
<ZipCPU> Well, okay, cool, I'll stop checking there for posts to answer ;)
<ZipCPU> I'm guessing their plan was to switch to stack overflow for user help requests
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<az0re> So, I'm trying to add a code review, and the GitHub UI updates apparently removed the ability to add inline code reviews??
<az0re> I open the "files changed" tab of a PR, try to click on the blue plus sign that appears when you hover over a line, and now... nothing appears
<az0re> WTF GitHub
<Lofty> az0re: https://puu.sh/G98XX/871151c62f.png <-- still here for me
<az0re> Yup it doesn't work in Tor Browser
<Lofty> ...JS?
<az0re> Nope, fully enabled
<az0re> On "Standard" security level
<az0re> Fucking GitHub
<az0re> All for some UI changes that actually degrade the user experience
<az0re> There was another great instance today of the UI failing since the update: I viewed a repo and all commit messages, times, etc. were simply empty placeholders, presumably to be fetched by broken JavaScript later
<az0re> Why, GitHub, why?!
<az0re> The design team just had to change the UI to add some lines to their resume and convince management that they're actually adding value?
<az0re> Fucking infuriating
<az0re> Anyway, I can't participate in code reviews until this is fixed. If anyone here has a commercial support contract, please do open a ticket asking them to fix the code review interface on Tor Browser.
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<jmamish> I've been checking my designs by synthesizing (for ice40) with yosys, then dumping a synthesized version of my design with "write_verilog". I then run both my RTL design and the synthesized design in iverilog and compare results.
<jmamish> I've been checking my designs by synthesizing (for ice40) with yosys, then dumping a synthesized version of my design with "write_verilog". I then run both my RTL design and the synthesized design in iverilog and compare results.
<jmamish> This has helped me find a few dumb bugs, but it's obviously really really slow in iverilog (takes like 50 - 100x as long as the RTL design).
<jmamish> Is it pointless to run verilator instead on the synthesized design, or can I use verilator to speed up simulation of the synthesized design?
<whitequark> verilator should speed it up
<whitequark> you could use cxxrtl as well
<jmamish> Thanks whitequark. I'll check out cxxrtl.
<jmamish> is it possible that some of the simplifications that verilator makes will make it pointless to compare the RTL to the synthesized design? I don't think it will be the case, but...
<whitequark> i've never looked closely at verilator, but i know that for single clock synchronous designs, cxxrtl will be an exact match to your hardware if you do pass timing
<whitequark> i'm fairly sure this is also true for verilator
<jmamish> Awesome. Thanks.
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