clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<trabucayre> I encounter a problem to simulate ECP5 code with specific hardware IP. see https://pastebin.com/b3QMWK37 The problem is not iverilog or my code but seems to be due to include problem. The missing file is present at the same level as cells_sim.v but not seen.
<tpb> Title: iverilog -s testbench -o ecp5evndemo_tb.vvp ecp5evndemo_tb.v ecp5evndemo.v `yosy - Pastebin.com (at pastebin.com)
<daveshah> There is a blackbox for USRMCLK in cells_bb.v
<trabucayre> I suppose i'm wrong somewhere but where.
<trabucayre> Yes and this one is in cells_bb.v
<trabucayre> ok I need to add this file one.
<trabucayre> due to the "Include file cells_ff.vh not found" I'm bit lost
<daveshah> You need /usr/local/share/yosys/ecp5/ to be in the iverilog include path
<trabucayre> It's work better! thanks
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<aaaa> can yosys take switch-level verilog and reduce it to gate-level (even if inefficient)
<aaaa> (switch level being pmos / nmos )
<DaKnig> how does switch level verilog look?
<DaKnig> isnt it a bunch of primitives?
<aaaa> pmos pmosA(out_net, 1, a);
<aaaa> pmos pmosB(out_net, 1, b);
<aaaa> pulldown pup(out_net);
<aaaa> like this
<aaaa> its primitives, but they're verilog builtins
<DaKnig> then yosys would need to know how those "modules" behave
<aaaa> yosys seems to be accepting them
<aaaa> but opt/techmap/abc don't seem to acknowledge them
<aaaa> wait nvm
<whitequark> aaaa: no, as per https://github.com/YosysHQ/yosys/#unsupported-verilog-2005-features these are not supported and never will be
<tpb> Title: GitHub - YosysHQ/yosys: Yosys Open SYnthesis Suite (at github.com)
<DaKnig> what model are you even using to simulate pmos transistors? there are so many; I doubt a digital simulator/toolchain can understand this correctly in all cases
<awygle> they're not real transistors. the verilog standard defines the model
<awygle> at least that's my understanding
<DaKnig> ah. I see.
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