clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<z0ttel> I have an issue with yosys complaining about directionality of a port:
<z0ttel> wire valid_output; assign valid_output = ...; assign out.valid;
<z0ttel> Oh, sry, there's something missing there
<z0ttel> wire valid_output; assign valid_output = ...; assign out.valid = valid_output; / / out.valid is an output port.
<z0ttel> That construct is rewritten to something where the following appears in the write_verilog result: assign valid_output = out.valid;
<z0ttel> (Which breaks the smt2 backend)
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<z0ttel> The above description is wrong. Apparently there's a problem with SV interface parameters in the module naming.
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