<cr1901>
Need a verilog language lawyer here... is "wire [3:0] foo = bar[3:0];" a legal initialization? The lack of assign bugs me
SpaceCoaster has joined ##openfpga
azonenberg_work has quit [Ping timeout: 245 seconds]
<whitequark>
cr1901: yes, 1364-2005 6.1.1
<cr1901>
Thanks, I'll take a look in a bit. Was looking at someone else's code and that caught me by surprise
m4ssi has joined ##openfpga
m4ssi has quit [Ping timeout: 245 seconds]
Bob_Dole has quit [Read error: Connection reset by peer]
SpaceCoaster has quit [Ping timeout: 246 seconds]
noobineer has quit [Ping timeout: 252 seconds]
sgcarnaval has quit [Ping timeout: 252 seconds]
noobineer has joined ##openfpga
SpaceCoaster has joined ##openfpga
mkdir has joined ##openfpga
<mkdir>
huddo again
<mkdir>
What is a good way to learn Verilog HDL? Any book recommendations?
dj_pi has quit [Ping timeout: 246 seconds]
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
<whitequark>
my personal view is that Verilog is a language awful enough that it should never be used for developing hardware
marshallh has quit [Read error: Connection reset by peer]
<whitequark>
it is, admittedly, a bit extreme.
<mkdir>
lol
<mkdir>
idc, we all got our opinions. I'm a newb so can't judge at all
<mkdir>
So you only use VHDL then?
<mkdir>
or only prefer
<mkdir>
whitequark: also it seems I can only use Verilog for my ice40 with the opensrc yosys + nextpnre
<whitequark>
mkdir: I never used VHDL
<cr1901>
verilog is what is used in FOSS world. VHDL is a much more complicated language, and there isn't really a good solution to make yosys parse it
<cr1901>
or RTLIL in the case of nmigen, _finally_ breaking that dependency
<whitequark>
yeah. there's a number of HDLs that aren't Verilog and avoid its mistakes, like HardCaml, Chisel, or nMigen
<cr1901>
Dunno what HardCaml does, but AFAIK Chisel targets FIRRTL. Does yosys know how to parse that?
<mkdir>
but I was wondering if there is a better reference
<cr1901>
I don't actually know a good reference. I learned Verilog from a Uni class, slowly correct the Altera-specific stuff over time from various tutorials
<cr1901>
I would not say that's a good way to learn Verilog
<whitequark>
cr1901: only write_firrtl, actually
<whitequark>
but you can convert it to verilog, of course, it's not like xilinx can do it
<mkdir>
cr1901: I see...
<mkdir>
there seem to be better references for vhdl
<mkdir>
I also have digital design and computer architectures Harris & Harris, it's very good but far more theory based
Bike has quit [Quit: Lost terminal]
futarisIRCcloud has joined ##openfpga
SpaceCoaster has quit [Ping timeout: 245 seconds]
rohitksingh_work has joined ##openfpga
mkdir has quit [Remote host closed the connection]
cr1901 has quit [Quit: Leaving.]
cr1901 has joined ##openfpga
SpaceCoaster has joined ##openfpga
rohitksingh has joined ##openfpga
Bob_Dole has joined ##openfpga
mearon has quit [Ping timeout: 246 seconds]
mearon has joined ##openfpga
rohitksingh_wor1 has joined ##openfpga
rohitksingh_work has quit [Ping timeout: 245 seconds]
rohitksingh has quit [Ping timeout: 246 seconds]
rohitksingh has joined ##openfpga
s_frit has quit [Remote host closed the connection]
s_frit has joined ##openfpga
sgcarnaval has joined ##openfpga
<whitequark>
hm, who did I discuss boneless here with?
<whitequark>
q3k: sorear: marcan: daveshah: i fixed the last outstanding issue in boneless. namely, that i wanted to use the ALU for computing both PC *and* Rd, but this didn't work so well for JAL
<whitequark>
namely, JAL needs to compute PC+1+imm (to jump there), but also PC+1 (to store to Rd)
<whitequark>
of course, I could make the next-PC mux one level deeper, and thread the result of the PC+1+imm adder there, but it felt... really gross
<whitequark>
so I decided to make it a multicycle instruction
<whitequark>
*first* it computes PC+1 and stores it to Rd, and *then* it computes PC+1+imm, and jumps ther
<whitequark>
in an FSM implementation it's like one more flop, and in a pipelined implementation it's a wait state (which I need anyway because of multicycle shifts)
ironsteel has joined ##openfpga
Miyu has joined ##openfpga
<whitequark>
interestingly, JALR isn't nearly as easy to implement
<whitequark>
but it's OK, it can just be a pseudo that expands into two instructions. it's a pretty rare instruction, only really useful for virtual calls, and it's not like there will be a ton of those
<ironsteel>
lots of example projects and a good reference. Also ZipCPU's tutorial is really nice: https://zipcpu.com/tutorial/
OmniMancer has joined ##openfpga
Asu has joined ##openfpga
edmund_ has joined ##openfpga
rohitksingh_work has joined ##openfpga
rohitksingh_wor1 has quit [Ping timeout: 272 seconds]
m4ssi has joined ##openfpga
<q3k>
whitequark: honestly, any time i implemented a CPU i always had a static (PC+1) adder in addition to the main ALU
<q3k>
whitequark: but yeah if you're going for surface area that's no good
<q3k>
(well, not PC+1, but next_pc, so PC+4, because I only did const instruction width stuff)
<q3k>
but yeah it's wasteful
<q3k>
multicycle might be the way to go
Asu is now known as Asinou
<whitequark>
q3k: oh I mean besides the PC+1 adder
<q3k>
can you not (ab)use that?
<whitequark>
q3k: I could integrate the mux between PC+1 and PC+1+imm into the adder, yes
<whitequark>
unfortunately, then I need another mux for JR
<whitequark>
so it's actually nicer to have one mux between PC+1 and ALU result, and then the address calculation also becomes a whole lot less restricted
rohitksingh has quit [Remote host closed the connection]
rohitksingh_wor1 has joined ##openfpga
rohitksingh_work has quit [Ping timeout: 245 seconds]
rohitksingh_wor1 has quit [Read error: Connection reset by peer]
<ZipCPU>
ironsteel: Thanks! o/
rohitksingh has joined ##openfpga
finsternis has quit [Excess Flood]
finsternis has joined ##openfpga
rohitksingh has quit [Ping timeout: 272 seconds]
rohitksingh has joined ##openfpga
renze has quit [Quit: Spaceserver reboot?!]
pie_ has quit [Ping timeout: 258 seconds]
Laksen has joined ##openfpga
genii has joined ##openfpga
SpaceCoaster has quit [Quit: ZNC 1.6.5+deb1+deb9u1 - http://znc.in]
SpaceCoaster has joined ##openfpga
vonnieda has joined ##openfpga
m4ssi has quit [Remote host closed the connection]
davidc__ has quit [Ping timeout: 268 seconds]
emeb has joined ##openfpga
Laksen has quit [Quit: Leaving]
renze has joined ##openfpga
rohitksingh has quit [Ping timeout: 244 seconds]
OmniMancer has quit [Quit: Leaving.]
rohitksingh has joined ##openfpga
pie_ has joined ##openfpga
azonenberg_work has joined ##openfpga
pie_ has quit [Remote host closed the connection]
pie_ has joined ##openfpga
pie_ has quit [Remote host closed the connection]
pie_ has joined ##openfpga
pie_ has quit [Remote host closed the connection]
pie_ has joined ##openfpga
rohitksingh has quit [Remote host closed the connection]
Miyu has quit [Ping timeout: 268 seconds]
mumptai has joined ##openfpga
mumptai has quit [Quit: Verlassend]
emeb_mac has joined ##openfpga
genii has quit [Remote host closed the connection]
Asinou has quit [Remote host closed the connection]
Bike has joined ##openfpga
vonnieda has quit [Quit: My MacBook Pro has gone to sleep. ZZZzzz…]