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<hackerfoo>
I've started a new channel for anyone interested in HLS design e.g. how to map high level algorithms to hardware: ##hlsdesign
<whitequark>
hackerfoo: what if i'm interested in HLS design in a "how can we make HLS unnecessary" way
<hackerfoo>
whitequark: Why?
<daveshah>
The stuff I've played with in the past has been along the lines of automatically adding registers to meet timing and balance BRAM latencies, rather than wholesale rewriting of algorithms
<daveshah>
I think that's quite a nice spot, if not quite full HLS
<whitequark>
hackerfoo: HLS tends to be somewhat akin trying to force a square pin into a round hole
<hackerfoo>
What I'm interested is mapping algorithms that are in a language to formally reason about into provably correct hardware designs.
<whitequark>
even if you can transform an algorithm that was never written for logic synthesis into RTL, that's a tiny part of overall success
<hackerfoo>
whitequark: I agree if you're talking about C/C++ HLS.
<whitequark>
C/C++ is the most egregious example
<whitequark>
but it applies wider than just that
<whitequark>
I think any HLS that has the potential to be a truly good tool has to incorporate language design elements specifically targeting sequential logic
<hackerfoo>
The CPU model of computing is not appropriate for FPGAs.
<daveshah>
tbh, I think C++ isn't a bad base for a HLS (but I don't mean turning arbitrary C++ programs into hardware, instead a framework on top of C++)
<hackerfoo>
In my language, recursion gets mapped to sequential logic.
<keesj>
like systemc?
<daveshah>
Probably a bit higher level than that
<daveshah>
I am thinking more about pipeline type applications, so not convinced that recursion is a good fit
<hackerfoo>
Recursion works pretty well for pipelines.
<hackerfoo>
Are you familiar with lazy lists, as in Haskell?
<daveshah>
But the point is I don't want to specify pipeline latencies
<whitequark>
recursion to pipeline is an interesting approach
<hackerfoo>
I implemented recursion modulo cons, which allows handling streams like you'd handle lists in Haskell.
<daveshah>
It seems like quite a nice approach for high level HDL, but it doesn't seem like HLS
<hackerfoo>
I can show testbenches and traces if interested.
<hackerfoo>
Isn't HLS mapping a different abstract model to hardware?
<daveshah>
To me a big part of HLS is not specifying pipelines and latencies so explicitly
<hackerfoo>
There are non-C compilers that claim to be HLS.
<daveshah>
Sure, I even know of a Go-based HLS
<hackerfoo>
There are no explicit pipelines, but the translation is pretty predictable (to me.)
<hackerfoo>
For latency, I'm using ready/valid between recursive functions/modules.
<hackerfoo>
But maybe that could be optimized later if I can statically calculate the number of cycles.
<keesj>
to me VHDL suites fully my needs for the low level stuff. for the more complex stuff starting just at wishbone for me.. I think it .. like as usefull as assembly programming is today for 99.99% of the sutff
<hackerfoo>
For combinatorial logic (nonrecursive functions) there is no ready/valid logic.
<hackerfoo>
I was about to search, but is AXI suitable for a bus for open-source designs? I know it's royalty-free, at least.
<daveshah>
Well, plenty of open source designs use it
<daveshah>
istr there is a term that prevents you using it with non-Arm Arm-ISA CPUs, but I might be misremembering
<daveshah>
If area is more of a concern than performance I would probably prefer Wishbone
<hackerfoo>
One nice thing about hardware is that it's more modular than CPU code, you don't have to embed one language in another e.g. C and inline assembly, you just have to connect the wires/bus.
<whitequark>
sort of
<whitequark>
if you want to instantiate parametric modules in one language from another...
<whitequark>
you're kind of out of luck most of the time
<hackerfoo>
At some point, you just need all the right names for the wires, right?
<qu1j0t3>
heh
<qu1j0t3>
that's a very idealised/Platonic view, i think
<whitequark>
hackerfoo: you need the synthesizer to call back to you
<whitequark>
i think i can make yosys do it
<whitequark>
out of luck with something like vivado tho
<hackerfoo>
Is it a big deal to explicitly instantiate modules independently?
<whitequark>
yes if they're parameterized and interdependent
<whitequark>
sure, you can hack around it, but it limits the flexibility of the designs you can make
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<hackerfoo>
I see. So the languages need a way to pass parameters at compile time. Maybe generate something like a header that has the values of the parameters.
<daveshah>
It's almost totally disappeared, but it was a high level HDL we learnt at uni
<whitequark>
I've heard of it
<whitequark>
i'm going to need to investigate it before making any HLHDL features in nMigen
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<emily>
you should probably look into the "guarded atomic actions" model of BlueSpec et al too
<whitequark>
okay
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<sorear>
bluespec unfortunately does absolutely nothing shaped like “let the tool figure out pipeline depth based on gate delay”
<sorear>
bluespec can be mapped to rtlil-equivalents without any technology knowledge, which might or might not be a feature
<emily>
oh, you know things about bluespec?
<emily>
can you teach me, because i don't know about "guarded atomic actions" myself :V
<hackerfoo>
daveshah: Thanks, Ruby is interesting.
<whitequark>
sorear: technology knowledge?
<hackerfoo>
Popr is based on linear logic.
<sorear>
whitequark: delays for cells, wiring, etc
<daveshah>
This is something I am very interested in higher level tools being able to reason about
<daveshah>
There are many applications where there is little difference between 5 or 20 cycles latency, let the tool work it out
<daveshah>
My application at the time was some AR demos
<whitequark>
daveshah: have you seen the nmigen issue about flow?
<daveshah>
Just seen it now. Seems very close to what I want
<whitequark>
want to collaborate on it?
<daveshah>
Yes, quite possibly
<daveshah>
I need to plan out what I'm actually doing for the next few months though
<whitequark>
excellent
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<sorear>
emily: yes I know a few things about bluespec. tried to reimplement it, but i seem incapable of completing any project the last two years :/
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<GenTooMan>
sorear well that could be problematic. Perhaps it's not that you are incapable just need to change project scale? Divide and conquer I've heard is useful.
<pie__>
#wot hackerfoo is doing hardware with popr now? hardore
<pie__>
hardcore
<pie__>
lucky i checked scroll...
<emily>
sorear: *nods*
<hackerfoo>
pie__: Yeah, I've been for the last few months. I added a Verilog backend.
<emily>
sorear: I hear great things about stimulants.