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<
hackerfoo >
Great. Another bus.
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<
ZirconiumX >
Altera marketing (I presume): "We need to make our architecture seem better, so double the number of ALMs"
08:37
<
ZirconiumX >
Altera engineering: "But we can't fit that many in a tile"
08:38
<
ZirconiumX >
Altera marketing: "Just do it"
08:38
<
ZirconiumX >
Altera engineering:
*adds ten virtual LUTs that don't exist in hardware, and also makes the spacing between each virtual LUT 3 to make it seem even bigger*
08:39
<
ZirconiumX >
On the other hand, this is Altera, I shouldn't have expected anything less
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<
ZirconiumX >
mwk: the diagram Intel provide there lies :P
08:57
<
mwk >
*shrug* that's the default state of vendor documentation, isn't it
08:58
<
ZirconiumX >
True, yeah :P
08:59
<
ZirconiumX >
For example, an ALM has 8 inputs; a, b, c, d, e, f0 and f1. This is the kind of weirdness we're dealing with here
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<
ZirconiumX >
*e0, e1, f0, f1
08:59
* mwk
linked it for the "xilinx lutshaming" part
09:00
<
mwk >
"quick, write a document on how our insanely complex lut packing is better than xilinx"
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<
mwk >
... they what?
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