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<tnt>
Is there any better diagram of DSP slices of the ECP5 than TN1267 ? I mean the diagrams in there don't have signal names that matches the available primitives !?!? Who writes those docs.
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<OmniMancer>
daveshah: the database for routing muxes stores all the bits that are set to select which signal drives a given wire yes?
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<OmniMancer>
Hmmm, I should see what the anlogic tools do if you ask for a net with an impossible/non-existent connection
<daveshah>
tnt: I haven't even finished understanding the DSPs myself, let alone fuzzing them
<daveshah>
Basically it's just the minimal MULT18X18D at the moment
<daveshah>
They are very weird DSPs. Even have DDR registers and clock dividers inside them
<daveshah>
OmniMancer: Yes, that's right
<tnt>
daveshah: ok, that makes me feel better that I'm not the only one finding them rather obscure :p
<daveshah>
I think I started fuzzing the ALUs, but I think I've still missed some weird combination of bits in certain configurations
<daveshah>
I'm still not fully sure about preadders or fractured 9x9 mode
<daveshah>
Nor any of the different ways they can be cascaded
<OmniMancer>
seems incorrect pnl which contained non-existent pin had a warning occur but will still happily make empty bitfile
<TD-Linux>
ooh can I mplement a half clocked p4 alu?
<OmniMancer>
alas it also seems like some of the entries in the route might not produce bits by themselves
<OmniMancer>
or I just spelled it wrong :/
<OmniMancer>
or both, I suspect some of these are fixed connections
<OmniMancer>
daveshah: what exactly is meant by "fixed connections" in project trellis?
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<daveshah>
OmniMancer: pairs of wires that are always connected without setting any bits
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<OmniMancer>
ah
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<OmniMancer>
It seems as if each location has a set of "wires" named a0-7 b0-7 c0-7 d0-7 and some e's but I think these are intermediate names for fixed connections, on the plbs atleast they statically map to the A,B,C,D inputs on the LUTs in the slices
<daveshah>
That seems very plausible
<daveshah>
In fact I think that's the same as ECP5, just lowercase...
<OmniMancer>
the tools won't generate any bits if you only place this: x1y70_c1.x1y70_slice0_c0 in a route for example
<OmniMancer>
though that should be c0 there :/
<daveshah>
Oh, BTW, it's closer to xo2 than ecp5 but this presentation is very interesting
<daveshah>
Yeah, that sounds like a fixed connection
<daveshah>
Effectively just a link from routing fabric to the slice primitive
<OmniMancer>
though things appear to be behaving very strangely now if I change around the numbers :/
<daveshah>
It's possible that some of these fixed connections also control LUT permutation
<daveshah>
Lattice doesn't do this but I can see how one would
<OmniMancer>
it seems it might not especially care what the intermediate step is called, so long as you don't do a direct connection between them...
<OmniMancer>
hmmm, no it appears you can use c0 or c1 for the first slice and it will generate the same bits, but any other values it will not generate any bits
<OmniMancer>
most strange
<OmniMancer>
daveshah: so would the actual 1,2,6 tile routing connections be fixed connections within themselves? as in the beginning of the wire is always connected to the end and mid points?
<daveshah>
In the case of ECP5 they aren't represented as fixed connections; just a single wire that spans multiple tiles
<daveshah>
But it's entirely possible that they could be represented as such
<OmniMancer>
okay, are they dealt with by the routing graph stuff in libtrellis?
<daveshah>
They are dealt with by the normalisation scheme
<daveshah>
e.g. N3_V06S0003 means wire V06S0003 in a tile 3 up from the current one
<OmniMancer>
but they aren't explicitly in the database since they don't have any bits just the endpoints?
<daveshah>
Yeah
<daveshah>
there isn't a fixed connection either, because everything just refers to one wire
<OmniMancer>
ah
<OmniMancer>
indeed
<daveshah>
as opposed to other cases where you have two different named wires connected together
<daveshah>
usually used for connections between routing fabric (which uses generic names) and primitive pins (which use primitive-specific names)
<OmniMancer>
I think the naming in the pnl files for anlogic is already sort of relative
<daveshah>
That would make more sense
<daveshah>
I'm not sure why Lattice didn't use a scheme like that, tbh
<OmniMancer>
btw what counts as the "middle" of a 6 tile wire?
<OmniMancer>
ah, unless being 6 tiles up it jumps over 5 tiles so also connects 3 tiles up
<daveshah>
From memory it goes e.g. source; 2 tile gap; sink 1; 2 tile gap; sink 2
<daveshah>
so it spans a total of 7 tiles; the "6" refers to the number of tile boundaries crossed
<OmniMancer>
that makes sense
<daveshah>
i.e. span-1
<OmniMancer>
I suppose I can do some math on the xNyN used
<daveshah>
similar to how a 2 tile wire actually covers a total of 3 wires
<OmniMancer>
indeed, it goes both to the tile above and the next tile up
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<OmniMancer>
how many luts wind up being in one PLC in ECP5?
<daveshah>
OmniMancer: 8
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<OmniMancer>
I think the anlogic parts wind up with 4 regular ones and then 8 of the "extended ones" which come in pairs and can be used as two LUT4s or one LUT5 but the two LUT4s I suspect have to have the same input signals
<daveshah>
Interesting
<daveshah>
"two LUT4s I suspect have to have the same input signals" sounds like Xilinx LUT6s fracturable into two LUT5s, it's quite a standard arrangement
<OmniMancer>
yes
<OmniMancer>
and then the usual logic to chain them further
<ZirconiumX>
And like the Cyclone V "fake LUTs"
<OmniMancer>
That sounds intriguing?
<ZirconiumX>
The fake LUTs?
<ZirconiumX>
OmniMancer: ^
<OmniMancer>
yes
<OmniMancer>
what is fake about them?
<OmniMancer>
ZirconiumX: ^
<ZirconiumX>
OmniMancer: so, I think it's a leaked implementation detail. A Logic Array Block (LAB) contains ten Adaptive Logic Modules (ALMs), but Quartus exposes twenty locations for the LUTs. Obviously, two locations map to the same ALM; thus the term "fake LUTs"
<ZirconiumX>
Because Quartus can pack multiple independent LUTs into an ALM
<ZirconiumX>
e.g. two LUT4s, a LUT5 and a LUT3,
<OmniMancer>
Ah so it has more than one output from the multiplexer mess but the functions have to share inputs I guess
<OmniMancer>
Tomorrow perhaps some mysteries can be solved, it might be best to just ask the router to route some signals between two placed instances and record the resulting route and bits and try to correlate from that
<ZirconiumX>
OmniMancer: not necessarily; the ALM, while being a LUT6 has 8 inputs and 4 outputs, so while bigger shared functions have to share input terms, it's not *quite* as bad as that.
<OmniMancer>
Ah okay, that is interesting and also quite annoying for working out how much space stuff takes
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<ZirconiumX>
OmniMancer: Intel's marketing department seem to indicate they can fit the equivalent of 2.5 LUT4-based LEs in an ALM. While I don't think that's entirely true, you could definitely fit 2 independent LUT4s in there
<OmniMancer>
cool
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<_whitenotifier-f>
[libfx2] jedrzejboczar commented on issue #2: cdc-acm example: port disabled by hub - https://git.io/Jea84
<_whitenotifier-f>
[libfx2] jedrzejboczar closed issue #2: cdc-acm example: port disabled by hub - https://git.io/JeEvx
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