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<sensille> i use the following construct in yosys: https://pastebin.com/0iC8L6Zm
<sensille> with i = NDAQ to simulate a loop break
<daveshah> afaik that won't work with how Yosys unrolls for loops
<sensille> yosys doesn't complain, but it looks like it still runs through the full loop
<daveshah> yeah, it should complain
<daveshah> the solution is to have another register that you ' = 0' at the start, ' = 1' when you have a match, and add as an extra condition to the if statement
<sensille> it took me many hours of desperation to find that. of course in simulation it works
<sensille> register? or integer?
<daveshah> reg is fine, because it needs to be 1 bit only
<sensille> strange, it won't be a register in hardware ...
<daveshah> reg in verilog doesn't mean register
<sensille> well, that's verilog for me :)
<sensille> ok, thanks
<daveshah> it just means assigned in an always block rather than using an assign statement (similar to how you still use reg with always @*)
<sensille> i guess that was one more point for post-synth simulation
<sensille> i probably can't do that with verilator, though
<sensille> of course now verilator complains about a blocking assignment
<sensille> (which can be disabled)
<sensille> interestingly though it didn't about the previous construct
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