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<promach3>
keesj: I do not quite understand why there are 3 timing scenarios for `DQS` , I suppose `DQS` are generated from `CK` ?
<promach3>
So, I think `DQS` == `CK` ?
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<promach3>
keesj: I think there is a mistake in the Micron document. `Command` signal is aligned with `CK` , not 90 degree out-of-phase with respect to `CK`. Please correct me if wrong
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<promach3>
For DDR3 memory controller. See DQS and DQ signal pair which is basically DDR (require both posedge clk and negedge clk)
<promach3>
As for CK and Command bus signal pair, I have a side question: do these two signal require 90 degree phase shift as DQS and DQ signal pair ?
<promach3>
In other words, should Command bus signal be strictly aligned with CK , not 90 degree out-of-phase with respect to CK ?
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<keesj>
promach3: with DDR3 the idea is that not all chips need to be at the same distance from the host e.g. their "fly by" technology. with that in mind the time it will take for different chips to return the signal will take different amount of time and be at a different "place" within the master clk. the CLK can not really be used to sample the data signal. there is a differential signal the DQS that travels
<keesj>
the same lenght as the data signal that can be used for that purpose.so.. There is a relationship between clock and the DQS but I would read CLK like an aproximation of when to read the data and the differentuial DQS .. the moment. there is an app note from xilinx on implementing ddr3 using the serdes2 .. that one was pretty nice for me to understand the different timings
<keesj>
I .. have read XAPP1017 (v1.0) July 22, 2016 and XAPP1064 (v1.2) November 19, 2013 both quite nice to understand how a ddr3 controller can be implemented when using an FPGA