pepijndevos changed the topic of #apicula to: Project Apicula: bitstream documentation and tooling for Gowin FPGAs https://github.com/YosysHQ/apicula -- logs https://freenode.irclog.whitequark.org/apicula
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<trabucayre> fuck. Tried to add gw1ns-2c but:
<trabucayre> ERROR: Found two arcs with same sink wire R15C15_A0: ctr_d[10]_LUT2_F_I0[1] (4) vs ctr_d[13]_LUT2_F_I0[3] (1)
<trabucayre> :-(
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<gatecat> trabucayre: looks like two LUTs might have ended up with overlapping routing?
<trabucayre> gatecat: yep. But to debug that...
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