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<marcan>
whitequark: so I was thinking about how to do pin expansion for revC, to do large pincount introspection/reversing when you control the target (i.e. slow clock)
<marcan>
have you thought about that kind of thing?
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<whitequark>
yeah
<whitequark>
i'm slowly reverse-engineering the ATF1500 CPLDs
<marcan>
oh you want to use a CPLD?
<marcan>
I was thinking of a pile of 74xx logic
<marcan>
I guess you'd need a tristatable latch and a tristatable buffer per 8 pin group of pins, or something like that
<marcan>
to do I/O
<tnt>
Heh I use LP384 for that nowadays. I guess to each his own :)
<marcan>
I'm thinking something like wanting to control ~100-160 pins
<marcan>
but in sensible chunks
<sorear>
sounds like provisioning 160 level shifters would be interesting
<whitequark>
tnt: well, most things that require large pin counts IME also require 5V
<whitequark>
or at least, enough of them do that an expander should do 5V
<whitequark>
marcan: yeah i think a CPLD is ideal
<whitequark>
admittedly, atf1500 is literally scraping the bottom of the barrel
<whitequark>
they killed the dual IO bank / 1.7-5.5 version of it (ATF150xBE) so it's even less useful than I hoped
<awygle>
160 level shifters isn't that bad provided you don't need individual directional control. Glasgow, of course, does.
<whitequark>
indeed, so with ATF1502 i can just stuff a giant shift register inside.
<whitequark>
i mean, i can actually do it with the vendor tools and just stuff a binary into the tree, but it feels wrong :o
<awygle>
It turns out to be about 10-12 chips, otherwise.
<whitequark>
*:p
<awygle>
Heh, yes. Wait so if the dual IO is dead, how will it work with 5V? Put on the other side of the 5V Glasgow shifters?
<tnt>
whitequark: but then it's 5v only right ?
<whitequark>
it is 5v only *vcore*, but *vio* can be 3-5
<whitequark>
which is totally backwards
<tnt>
oh ok, I missed that.
<awygle>
I love old logic lol
<whitequark>
they have a really confusing set of dice
<hell__>
what about xc9572xl series cplds? up to 100 pins and they are dirt cheap
<awygle>
I was considering this exact use case last night (night before?) because of byuu's blog post
<whitequark>
one for 3-5 Vio 5 Vcore, one for 3 Vio 3 Vcore but it's faster
<whitequark>
and they also have "low power" variants of both
<awygle>
With cr1901
<whitequark>
which has not been within two orders of magnitude of what people consider "low power" for a decade
<whitequark>
hell__: they aren't true 5V devices
<whitequark>
they are only 5V tolerant
<awygle>
So I'm interested in what you come up with
<hell__>
right
<whitequark>
this means you can't drive logic with them that has Vih >2V or so
<tnt>
Didn't lattice have 5v cpld too ?
<awygle>
EoL
<whitequark>
tnt: they did, machxo...
<whitequark>
but yes, eol
<whitequark>
very confusingly explained on the website
<whitequark>
also
<whitequark>
iirc they weren't true 5v either, let me look it up
<hell__>
there's the non-XL cousins as well, which i think use 5V, but I don't know if they are worth the hassle
<whitequark>
non-xl ones are unobtainium
<hell__>
oh
<tnt>
I thouch some ispmach had 5v
<whitequark>
er, ispmach5, sorry
<marcan>
whitequark: for the use case I was thinking of I don't need individual direction control
<marcan>
just bankwise
* hell__
has two non-xl on some ultra-thick server PCBs
<whitequark>
tnt: ok so the thing is, it's buried in the datasheet
<marcan>
it's for old console logic, so the only I/O things are going to be data buses really
<whitequark>
but it has Voh=3.6V on 5V devices
<whitequark>
they do this because it has 1 bank
<awygle>
marcan: are you also looking at snes ppu stuff lol
<whitequark>
so it has to coexist with 3V and 5V devices at the same time
<whitequark>
in the same bank
<marcan>
awygle: yes lol
<marcan>
I was talking with byuu about this
<marcan>
this stuff really shouldn't be Hard™
<whitequark>
marcan: well, are you ideologically opposed to CPLDs here?
<awygle>
So was I. I'm a bit booked up atm, but marchish I should have time.
<marcan>
I'm not, if the parts are available
<marcan>
and we can stack enough
<awygle>
Happy for you to beat me to it tho.
<marcan>
awygle: same.
<whitequark>
marcan: thousands if not tens of thousands of them at every usual distributor
<marcan>
no time until march lol
<whitequark>
and they are in active production
<awygle>
Well in that case, ping me here or on Twitter when you want to get started and we can join forces
<marcan>
CPLDs are nice because it makes the whole thing super flexible
<marcan>
so sure
<marcan>
awygle: ack
<whitequark>
but note, only for 150[248]ASV?L? parts
<whitequark>
ATF1500 and ATF150xBE are dead for godo
<whitequark>
just FYI because this is confusing
<awygle>
whitequark: is the ATF reversing a priority for you, or has it rotated towards the bottom of the Infinite Yak Ring Buffer?
<marcan>
so 32 macrocells, assuming you use an 8bit bus and 4 control pins, that's 20 IOs you can stuff into one of them
<marcan>
not bad I guess
<whitequark>
also, i already hacked off the useless toolchain parts, now it's 5 files that run on wine
<marcan>
maybe use an extra one to do address decoding for the rest
<whitequark>
marcan: you can get larger ones
<whitequark>
1508 is 128 MC
<whitequark>
they optimistically planned to fab 1516 an i think 1532 but i don't think silicon of those ever existed
<marcan>
oh, the 160 pin one has them all broken out?
<marcan>
that's a cool one then
<marcan>
at that point I'd just make stackable boards
<marcan>
all 16 glasgow I/Os to one end, 112 I/Os out the other
<marcan>
and program them with an address or something
<whitequark>
no, it stupidlu has only 84 actual IO
<marcan>
wha
<hell__>
wut
<whitequark>
it has a shitton of NC pins
<whitequark>
for reasons i can't comprehend
<marcan>
I count 91 or something?
<whitequark>
wait, sorry, not 84
<whitequark>
96?
<marcan>
yeah
<marcan>
ok so you get 80 I/Os per board
<marcan>
still nice
<whitequark>
yup
<whitequark>
the 5V version works at 125 MHz which is pretty ok
<marcan>
more than enough
<whitequark>
the 3V version works at uhm
<whitequark>
77 MHz?
<whitequark>
I swear it was faster when I looked at it before
<awygle>
How does one estimate logic capacity for CPLDs? I have never really worked with them, is there a wrong-but-useful macrocell to LUT conversion factor?
<whitequark>
oh, it was *BE* that can do 333 MHz
<whitequark>
BE is technically still in production but no one stocks them and mouser says NRND
<whitequark>
so i assume microchip's website is wrong or something
<whitequark>
awygle: 08:26 < awygle> whitequark: is the ATF reversing a priority for you, or has it rotated towards the bottom of the Infinite Yak Ring Buffer?
<marcan>
then you can use it as a giant EXTEST thing, or per-pin controls with only a fraction of the pins available, or a design with blockwise control
<whitequark>
do you think we could free up the 12V trigger so that it actually controls OE1?
<whitequark>
e.g. make it that it only triggers on power cycle
<marcan>
then to make it stackable... do some chaining of the JTAG pins and use that for chip select during normal operation too?
<marcan>
hm
<marcan>
that would be interesting
<whitequark>
seems that could make it significantly more elegant
<whitequark>
at no real loss in functionality
<marcan>
like apply 12V on power cycle, clear it when a pin goes high, for example?
<marcan>
should be doable
<whitequark>
I'd say apply 12V on power cycle if OE1 is high, have it pulled low
<whitequark>
same idea, maybe slightly more robust?
<marcan>
there's a race condition there
<marcan>
it has to be 12V = low
<marcan>
because the glasgow IOs will be low without power
<whitequark>
oh, yeah
<marcan>
and the pull has to be low
<whitequark>
yes, I agree your proposal makes more sense
<whitequark>
and in fact is the only possibility
<whitequark>
08:54 < whitequark> same idea, maybe <<a lot less>> robust?
<whitequark>
ok, so that means OE1 naturally becomes some sort of sync signal, like ~CS
<whitequark>
or rather just CS
<whitequark>
seems fine
<whitequark>
"something you will use, active high, when you reuse JTAG pins"
<marcan>
yeah
<marcan>
so initial low = 12V
<marcan>
high = 0V
<marcan>
subsequent low = 5V
<marcan>
or something like that?
<marcan>
so we invert that pin
<marcan>
could be done not inverted too of course
<marcan>
initial low 12V, high = 5V, low = 0V
<marcan>
depends on how we design that circuit
<whitequark>
not inverting seems like it'd avoid gotchas
<marcan>
sure
<marcan>
then for JTAG, I guess just build a TDI->TDO chain, and then you can do the following
<marcan>
use a jumper to close the loop at the top
<marcan>
for 1 board, you get two IOs there, in whatever direction you want
<marcan>
for 2 boards, you get one IO to each board, plus an internal link between them if you care to use it for anything useful
<marcan>
for 3 boards, you can actually build an encoder: top board forwards down, bottom board forwards up, middle board enables only if top/bottom are disabled
<marcan>
and honestly if you need to address more than 3 boards you should start using a shift register there anyway, and presumably you're slow enough on everything to stop caring at this point
<whitequark>
you can still update them at what, 100 khz?
<marcan>
sure
<marcan>
I think this even works for 4 boards for all combinations?
<marcan>
yeah it should
<marcan>
so yeah this makes addressing possible without any switches or weirdness, just using JTAG with (slightly) different designs and a fixed wiring pattern there
<whitequark>
yep
<whitequark>
for synthesis i should add upstream support to yosys
<whitequark>
it's like 1-2 days
<marcan>
heh
<whitequark>
it's literally just simplemap and dff whatever
<whitequark>
the fitter is smart enough you don't need to run abc
<whitequark>
in fact, the god damn thing is way too smart to conveniently fuzz
<whitequark>
ok wait hm
<whitequark>
no, nevermind, should work fine
<hell__>
tnt: right, but afaik that was technically required
<hell__>
you can also erase all kinds of ROMs if you use even higher voltages
<whitequark>
marcan: how would you actually design the trigger circuit?
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<marcan>
whitequark: haven't thought of it yet :-)
<whitequark>
note, i think we don't actually need 12V specifically
<marcan>
I assume it's one of those 9V or higher things?
<hell__>
oO(add a RS232 port to Glasgow, which would need a MAX232 or similar)
<marcan>
lol
<hell__>
then use that chip's charge pump for 12V
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<whitequark>
marcan: yeah i think so
<whitequark>
at least, a voltage doubler would 100% work
<whitequark>
and also it doesn't use that voltage for actual programming
<marcan>
obviously
<marcan>
LTC1262 is designed for this apparently
<whitequark>
ouch, linear
<marcan>
I do wonder if this is one of those things you can design with a 555 and a transistor or something :p
<marcan>
like the whole trigger circuit, not just the pump
<whitequark>
probably sorta? reducing part count is still helpfu
<hell__>
^ this is why i thought of adding a rs232 level shifter, can also be used as, you know, for actual rs232 stuff
<whitequark>
no maxim parts
<hell__>
though it might not be worth the hassle, most things signal stuff at lower voltage levels
<tnt>
whitequark: So your pulse on In, does it meet the 7V Vih_min ?
<marcan>
so connect Vdd to B?
<marcan>
also I was thinking of asking twitter lol
<whitequark>
tnt: ah fuck's sake
<marcan>
and yeeeah
<marcan>
cmos chips be like that
<marcan>
whitequark: pull-up on S1/S2 to Vdd, diode to A?
<marcan>
wait no that won't really work
<marcan>
since there's a pulldown
<whitequark>
there's a third switch
<whitequark>
we can use it to control SD
<marcan>
true
<whitequark>
hm
<whitequark>
so let's redo this
<tnt>
If you shutdown the 10V psu, how does the mux work ?
<whitequark>
diode
<tnt>
oh right, I missed that.
<whitequark>
:p
<whitequark>
most clever bullshit i've ever done
<whitequark>
i think
<marcan>
I feel like this is the kind of thing where some bullshit might bite us in the ass a la i2c mux, so I wouldn't dare spin it without a prototype
<marcan>
but the idea looks good
<marcan>
er, i2c shifter
<whitequark>
sure
<tnt>
The other thing I see could be an issue is A1 being 5V, if the 3u3 cap doesn't discharge fast enough to have 5V being registered as a high input.
<whitequark>
yes, already realized it when you mentioned Vih
<marcan>
whitequark: so is there a reason to even shut down the charge pump at that point, btw?
<whitequark>
... uh
<marcan>
might as well leave it at 10V and ensure the switch has tons of headroom for the pass transistor to pass 5V
<marcan>
and then you might as well make A1 10V
<marcan>
also the diode thing doesn't work lol, it would still hold the thing low
<marcan>
maybe a transistor and flip the sign of everything, or maybe several diodes
<marcan>
or an LED if you want to be funny
<whitequark>
marcan: use two resistors
<whitequark>
ah, hm, not quite as simple
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<electronic_eel>
about the 10v mux circuit puzzle: must there really be low impedance path in both directions between in and out after the first pulse, or would it be enough if in is always high-z and out always the output?
<electronic_eel>
I just skimmed the discussion before, but I thought the out will be used for a output enable signal on a cpld. this would mean it is always an input on the cpld, so always an output on the mux/levelshifter circuit would be ok
<electronic_eel>
the output enable on the cpld just needs the different voltage levels to activate programming mode on startup of course, so the mux circuit must always provide 10v on startup until the first pulse is sent on in
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