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berndj >
magic's drc complains when a substrate contact is less than 4 lambda from a diffusion contact, also that opposite diffusions are too close
18:08
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berndj >
but when i put the substrate contact directly adjacent to the diffusion contact, drc is happy. what gives? why is "opposite diffusions too close" not a problem then?
18:09
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berndj >
in both cases the intent is to strap the contacts together with m1. is it that magic's drc can't "see" that the contacts are strapped together, when there's a short m1 jumper connecting them?
19:35
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azonenberg >
Probably
19:48
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berndj >
whee, the dff simulates correctly!
19:49
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berndj >
not a full spice sim, just irsim's switch model simulation
19:50
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azonenberg >
On a somewhat related note
19:50
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azonenberg >
i want to make a tool for automatic recognition of standard cells at some point
19:50
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azonenberg >
In other words, given optical or secondary electron images of each layer
19:51
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berndj >
that sounds hard :-/
19:51
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azonenberg >
generate vectors
19:51
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azonenberg >
(possibly after manually drawing the boundary of each cell)
19:51
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azonenberg >
then extract transistors from the vector images
19:51
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azonenberg >
and so a behavioral (not necessarily SPICE-level since process details are unknown) simulation with all possible inputs
19:51
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azonenberg >
and maybe some heuristics to speed things up
19:51
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azonenberg >
to determine "this is a NAND3"
19:52
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azonenberg >
"this is a positive edge triggered dff"
19:52
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berndj >
that last step is the one i don't even know how i don't know how to do it
19:52
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azonenberg >
Basically, right now the first step in REing a standard cell chip is manually figuring out what each cell does
19:52
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azonenberg >
i'd like to automate that
19:53
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Sync_ >
yeah that's a good idea ;)
19:53
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azonenberg >
say "this is a cell", highlight it
19:53
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azonenberg >
five seconds later "NAND2x1"
19:53
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berndj >
would it be useful if you could at least find instances of common cells, regardless of their function?
19:53
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azonenberg >
degate can find cells once you higlight one instance and give it a name
19:53
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berndj >
"there's a cell here, and it's the same as the one here, here and here"
19:53
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azonenberg >
But it can't tell what is a cell
19:53
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azonenberg >
That would be a little harder but nice
19:53
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Sync_ >
oh degate can do that now
19:54
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azonenberg >
Degate also segfaults
19:54
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Sync_ >
yes it is good at that
19:54
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azonenberg >
whenever i try to add >1 layer in the last version i tried
19:54
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azonenberg >
i'm leaning toward writing my own tool
19:54
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azonenberg >
its too unstable :p
19:56
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Sync_ >
yeah it sucks
19:56
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azonenberg >
What I dream of is an IDA for hardware
19:56
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azonenberg >
something that takes in either an FPGA bitstream or die photos
19:57
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azonenberg >
does extractions and recognizes cells on the photos, reverses the bitstream
19:57
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azonenberg >
now you have a cell-level netlist
19:57
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azonenberg >
then do heuristics and isomorphism checking within neighborhoods to find higher level structures like adders and muxes
19:57
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azonenberg >
and perhaps even known hard IP blocks
19:58
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berndj >
hash it all and make a rainbow table!
19:58
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Sync_ >
oh actually, have y
19:58
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Sync_ >
wrong channel
19:59
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azonenberg >
berndj: lol
20:00
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azonenberg >
seriousl, it would be awesome to take in die images and have it automatically find "functions" like ida does
20:00
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azonenberg >
but they're standard cells
20:00
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azonenberg >
then find higher level structures
20:00
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azonenberg >
and "decompile" the result to generic RTL
20:00
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azonenberg >
one module at first, you could then split stuff off as you saw fit
20:01
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Sync_ >
I wonder when chip manufacturers will start to implement measures to stop people FIB from the bottom of the die
20:03
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azonenberg >
well 3D stuff is going to be a big PITA to reverse :p
20:08
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Sync_ >
yeah but that's not too popular :P
20:08
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Sync_ >
having annoying structures on top is
20:09
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Sync_ >
and I finally made some progress in metalization
20:13
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berndj >
what's #D stuff going to do to power densities?
20:14
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berndj >
aargh shift key! i mean 3D stuff
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