azonenberg changed the topic of #homecmos to: Homebrew CMOS and MEMS foundry design | Wiki: http://homecmos.drawersteak.com/wiki/Main_Page | Repository: http://code.google.com/p/homecmos/ | Logs: http://en.qi-hardware.com/homecmos-logs/
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<azonenberg> putting together a proposal to offer this class in the spring, any ideas?
<Sync__> pretty steep learning curve :D
<azonenberg> You think it's too fast? What material would you spend >1 lecture on that is currently down as only 1?
<Sync__> well, going from no idea to extracting a schem in 5 weeks is pretty hard imho
<azonenberg> Perhaps, but i need something more concrete
<azonenberg> Is there material i should cover that i don't have there?
<azonenberg> is there something i'm not spending enough time on?
<Sync__> how long are the lectures?
<berndj> azonenberg, are you assuming that students would be familiar with the switch model for FETs?
<azonenberg> berndj: Yes
<berndj> depending on what knowledge / skill you assume, i think asking students to figure out what a cell does might be a bit hard so soon into the classes
<azonenberg> Switch only, not assuming any knowledge of layout or analog characteristics
<berndj> obviously also depends on the cell
<azonenberg> the latter are beyond the scope of the class, and the former will be introduced
<azonenberg> I'd do simple cells
<azonenberg> like NAND4 or something
<berndj> ok
<azonenberg> then maybe a flipflop for extra credit
<berndj> i was just thinking that some of the memory element cells could be a bit tough
<azonenberg> oh, like a 6T SRAM?
<azonenberg> Yeah, not going to do that so early in the course
<berndj> how come SRAMs use 6 transistor cells but flipflops use loads more?
<Sync__> srams want to be fast
<berndj> even that dynamic d-type flipflop is 9
<berndj> flipflops aren't supposed to be slow :-/
<azonenberg> SRAMs include array logic and they normally have differential inputs/outputs
<azonenberg> the inverters etc don't count toward the 6 since you only include it at the edges of the array
<berndj> ok that's a handful right there in the inverters
<azonenberg> Yeah
<azonenberg> but those arent in the cell
<azonenberg> they're at the edges of the array
<azonenberg> An N-bit SRAM array isn't 6N transistors
<azonenberg> it's 6N + K*log(n) + M
<azonenberg> for some constants K, M that depend on the array geometry etc
<azonenberg> sorry, sqrt(n), not log(n)
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