nmz787_i has quit [Remote host closed the connection]
nmz787_i has joined #homecmos
Bike has quit [Quit: tire]
nmz787_i has quit [Ping timeout: 265 seconds]
pie_ has joined #homecmos
jamie has quit [Excess Flood]
jamie has joined #homecmos
Bike has joined #homecmos
jamie has quit [Excess Flood]
jamie has joined #homecmos
jamie has quit [Excess Flood]
jamie has joined #homecmos
jamie has quit [Excess Flood]
jamie has joined #homecmos
pie_ has quit [Ping timeout: 276 seconds]
gkwhc has joined #homecmos
<gkwhc>
Hey guys, this might be a bit offtopic, but still related to semiconductor development...there are different levels of design such as RTL, gate level... if im writing code that specifies the logic gate type/speed/slew rate/drive strength, what level would this be called?