08:46 <senilius> Even though the info maybe looking vague to you, it is the hardware which determines the behavior. Hence inter-CTA last lsu access wins, intra-CTA last lsu access fails from the two in done consequence/back to back.

08:47 <senilius> highly deterministic and not very black magic right, but then fences need not to be used.

08:50 <senilius> since that is deterministic using texture unit samplers and without one can instruct the chip to schedule with using few logic to do cache-distance based selection on a wfid row

08:51 <senilius> i forgat to mention that those two accesses go for the very same location of course

08:52 <senilius> then a FU becomes pinned to queues, and instruction is preloaded to register file to certain regs as indices

09:00 <senilius> even though some earlier chips are missing address calculator stride and base components, they still have index buffer arrays.

10:02 <rellla> omg, he's back.

10:11 <hellsenberg> oh dear

14:54 <sibelius> this index buffer stuff is more complex than using indirections having looked at the glsl_to_tgsi.cpp, be that abondened or not, just for reference for now, nicely documented.

14:56 <sibelius> it very much looks like hardware potention is intentionally handycapped by sw always, pretty enourmous stunts there to do that.

14:59 <sibelius> where comparison being, running hw on the very first gear or so to speak lobotomized way when kicking human terms in.

15:14 <sibelius> open source movement is doing a bad favor by following commercial stacks and the spec, actually there are bunch of talented or hardworking men around amongst you, probably they allready understand what the hw is actually capable of, it is just making hard for the users especially the communication with propriatery hw vendors

16:23 <sibelius> it drops the second access on intra-CTA cause one compute unit or SM equivalent only has single LSU, and the address calculator is done with continous assignment, however two accesses to the same location going to different CUs will apply the second access instead.

16:25 <sibelius> this can be demonstrated with a little verilog program. LSUs are instanced for global memory in CUDA for example, even though there are more texture units then global memory LSUs per SM clusters, texture based access is deprecated.

16:26 <anarsoul> sibelius: get lost

16:31 <sibelius> *than, but anyhow this is the major clue or hw inherent inevitably avoidable trick to real scheduling with some changes.

16:32 <sibelius> *unavoidable

16:39 <sibelius> this year i may do the prototype and guidelines how to lift various drivers to the glory, however i get exhausted too, tired about this all my own, can not really waste so much time anymore.

21:17 <rellla> wow, https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1151 and using the lowering with lima fixes 198 piglit tests

21:17 <rellla> http://imkreisrum.de/piglit/nir-algebraic-opts_lima/index.html

21:24 <anarsoul> rellla: I think it implements fall_equal but not in non-optimal way

21:24 <anarsoul> enunes should have more details

21:24 <anarsoul> btw I may have some time to work on cf next week

21:24 <anarsoul> hopefully I'll get it finished

21:29 <rellla> anarsoul: yes, it's because if fall_equal & co, and no

21:30 <rellla> i did not look into any details :)

21:31 <rellla> yeah, cf will be another thing that will fix many tests...

21:48 <anarsoul> btw gpir also lacks cf

21:48 <anarsoul> but I'm afraid I don't understand GP compiler well enough to implement cf

23:51 <anarsoul> rellla: looks like fs-cos-float regressed